Segmented Trench Gate MOSFET Structure for Ron-BVD Tradeoff
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Solution Overview
Problem
Conventional trench gate MOSFETs struggle to meet requirements for low on-state resistance (Ron) and high breakdown voltage (BVD) in power electronics applications.
Innovation Solution
The semiconductor device features an epitaxial layer with a trench gate structure comprising a bottom, middle, and top gate structure, each with a distinct gate dielectric layer thickness and gate electrode, allowing for separate biasing and modified work functions to optimize electric field profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional trench gate structure is used, then the device footprint is reduced and parasitic capacitance is lowered, but the on-state resistance cannot be sufficiently reduced while maintaining high breakdown voltage
Solution Approach 1:
The gate structure is divided into three separate gate electrodes (first, second, and third gate electrodes) positioned at different depths within the gate trench. This segmentation allows each gate electrode to independently control different regions of the channel, enabling optimized carrier injection and electric field distribution that reduces on-state resistance while maintaining breakdown voltage, all within a compact trench footprint.
Solution Approach 2:
Different gate dielectric layer thicknesses are applied to different gate electrodes: the first gate electrode has a thicker gate dielectric layer, the second has a moderate thickness, and the third has the thinnest gate dielectric layer. This local quality variation allows each gate electrode to be optimized for its specific function - the thicker dielectric for voltage control and breakdown protection, and the thinner dielectric for strong field effect and low resistance - thereby resolving the contradiction between low on-state resistance and high breakdown voltage in a small area.
2Ease of manufacture
If the gate dielectric layer thickness is uniform throughout the trench, then fabrication is simplified, but transconductance and electric field profile control are insufficient
Solution Approach 1:
The patent implements non-uniform gate dielectric layer thicknesses at different positions within the gate trench. The first gate electrode region has a thicker gate dielectric layer for enhanced breakdown voltage and voltage control, while the third gate electrode region has a thinner gate dielectric layer for stronger electric field effect and lower on-state resistance. This local quality differentiation optimizes transconductance and electric field profile control, achieving high performance while remaining manufacturable through selective deposition and etching processes.
Data Source
AI summary
A semiconductor device includes an epitaxial layer, at least one gate trench, and at least one trench gate structure. The gate trench includes a lower gate trench and an upper gate trench, and a width of the lower gate trench is less than a width of the upper gate trench. The trench gate structure is disposed in the gate trench, and the trench gate structure includes a bottom gate structure, a middle gate structure, and a top gate structure. The thickness of the second gate dielectric layer of the middle gate structure is less than the thickness of the first gate dielectric layer of the bottom gate structure. The thickness of the third gate dielectric layer of the top gate structure is less than the thickness of the second gate dielectric layer of the middle gate structure. The first, second, and third gate electrodes are separated from each other.