Power Semiconductor Device With Segmented Trench Gates
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Solution Overview
Problem
Existing power semiconductor devices face challenges in stabilizing switching characteristics and achieving high channel density, leading to unstable switch characteristics and low channel density due to uncontrolled parasitic capacitances.
Innovation Solution
A power semiconductor device structure is developed, combining closed cell and stripe cell configurations, with trench gates connected in specific patterns and doping concentrations optimized to reduce parasitic capacitances and enhance channel density, thereby stabilizing switching characteristics and improving robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional trench gate structures are used, then manufacturing is simpler, but switching characteristics are unstable and channel density is low
Solution Approach 1:
The gate structure is divided into multiple independent trench gates (first trench gate, second trench gate, third trench gate) with different orientations. The first and second trench gates extend in one direction while the third trench gate extends in a different direction, creating segmented regions that independently control carrier injection and reduce parasitic capacitance effects, thereby stabilizing switching characteristics.
Solution Approach 2:
The gate structure transitions from a single-direction linear arrangement to a two-dimensional grid-like configuration by introducing the third trench gate in a different direction. This dimensional change creates multiple current paths and distributes the electric field more uniformly, improving switching stability without significantly increasing manufacturing complexity.
2Quantity of substance
If conventional single-direction trench gates are used, then device structure is simpler, but channel density is low
Solution Approach 1:
The channel region is segmented into multiple zones by the differently oriented trench gates. The first and second trench gates create channels in one direction while the third trench gate creates additional channels in a perpendicular direction, effectively multiplying the channel density without requiring a proportional increase in device area.
Solution Approach 2:
Multiple trench gate structures with different orientations are merged into a single integrated device. The first trench gate, second trench gate, and third trench gate work together synergistically, with their combined effect producing higher channel density than the sum of individual gate contributions due to reduced parasitic capacitance at the intersections.
3Reliability
If parasitic capacitances are not controlled, then device structure is simpler, but switching characteristics are unstable
Solution Approach 1:
The harmful parasitic capacitances are effectively extracted or removed from the system by introducing the third trench gate in a different direction. This additional gate structure creates isolation regions that electrically separate adjacent channels, removing the parasitic coupling capacitance that would otherwise cause switching instability.
Solution Approach 2:
The third trench gate acts as an intermediary structure between the first and second trench gates. It mediates the electric field distribution and carrier flow between adjacent channels, preventing direct parasitic capacitance coupling while maintaining the beneficial low-on-resistance characteristics of the multi-trench configuration.
Data Source
AI summary
The power semiconductor device includes: a first trench gate and a second trench gate in a stripe shape extending in one direction in parallel and spaced apart from each other in a substrate; a third trench gate in a ladder shape extending in a direction different from the one direction between the first trench gate and the second trench gate in the substrate; a first conductive type body area each disposed between the first trench gate, the second trench gate and the third trench gate, respectively, in the substrate; a pair of first conductive type floating first areas surrounding each of bottom surfaces and at least one side of the first trench gate and the second trench gate in the substrate; and a first conductive type floating second area surrounding a bottom surface of the third trench gate in the substrate.