Segmented TRIAC Structure for High Commutating Capability

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Solution Overview

Problem

Current TRIAC semiconductor devices suffer from low commutability and operational deficiencies due to their single gate control mechanism, which limits their ability to effectively manage current flow in all quadrants.

Innovation Solution

The design incorporates a trench and isolation region in a TRIAC semiconductor device, separating it into two portions with distinct biasing conditions, allowing for separate current routing and preventing charge carrier migration between them, thereby enhancing commutating capability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single gate control mechanism is used in TRIAC devices, then the device structure is simple, but the commutating capability is low

Engineering Contradiction:
Improvedevice structureVSAvoidcommutating capability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the TRIAC device into two separate portions (first and second portions) with distinct gate terminals (first gate and second gate). Each portion can be independently controlled, enabling separate current routing and improved commutating capability. The trench structure physically separates the two portions while maintaining electrical isolation through the isolation region.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If a single gate control is used, then the device is easier to manufacture, but operational efficiency is limited

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidoperational efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The device is segmented into two independently controllable portions, each with its own gate terminal. This allows separate current routing and enhanced operational efficiency while maintaining a manufacturing process that integrates well with existing semiconductor fabrication techniques through the use of trenches and isolation regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each portion of the device has distinct local characteristics with separate gate controls, allowing optimized current management in different regions. The first portion can be controlled by the first gate while the second portion is controlled by the second gate, enabling independent optimization of each region's operational characteristics.

Inventive Principle:
Principle #3Local quality

3Reliability

If portions are separated with trenches and isolation regions, then commutating capability increases, but device complexity increases

Engineering Contradiction:
Improvecommutating capabilityVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The device is divided into two portions separated by a trench structure with isolation regions extending from the trench to the third silicon layer. This physical segmentation enables independent control and improved commutating capability while using standard semiconductor fabrication techniques to manage the added structural complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240204088A1Triac device with high commutating capability
Publication Date: 2024.06.20 LITTELFUSE SEMICON WUXI
  • US20240204088A1 patent drawing
  • US20240204088A1 patent drawing
  • US20240204088A1 patent drawing

AI summary

A semiconductor apparatus including first, second, and third silicon layers, the first silicon being coupled to the second silicon layer and the second silicon layer being coupled to the third silicon layer. The apparatus includes a trench formed in the first silicon layer and in at least a portion of the second silicon layer, an isolation region formed in at least the second silicon layer, where the isolation region extends from the trench to the third silicon layer. The apparatus also includes a first main terminal one and a first gate terminal coupled to a first portion of the first silicon layer, a second main terminal one and a second gate terminal coupled to a second portion of the first silicon layer, a main terminal two coupled to the third silicon layer, and one or more silicon regions in the first silicon layer and in the third silicon layer.