Segmented Tunnel Barrier Layer for Memory Cell Voltage Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor memory devices face challenges in reducing operation voltage, simplifying fabrication processes, and lowering fabrication costs due to limitations in the reliability and design of tunnel barrier layers used as selection elements in memory cells.

Innovation Solution

The implementation of a memory device with a tunnel barrier layer and an intermediate electrode layer, both divided into multiple portions in the first direction, overlapping with multiple resistance variable elements, which reduces current density and enhances the reliability of the tunnel barrier layer, allowing for lower operation voltages and simplified fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a tunnel barrier layer is used as a selection element in a memory cell, then the memory cell can achieve proper selection functionality, but the operation voltage remains high and the tunnel barrier layer reliability is insufficient

Engineering Contradiction:
Improvetunnel barrier layer reliabilityVSAvoidoperation voltage
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The tunnel barrier layer is divided into multiple separate portions along the first direction, with each portion overlapping with specific resistance variable elements. This segmentation allows current to be distributed across multiple paths, reducing the current density on each individual portion and enabling lower operation voltages while maintaining reliable selection functionality.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the tunnel barrier layer is divided into multiple portions, then the current density is reduced and reliability is improved, but the fabrication process becomes more complex

Engineering Contradiction:
Improvetunnel barrier layer reliabilityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple tunnel barrier portions are formed in a unified manufacturing process sequence, where the portions are created simultaneously or in an integrated manner rather than as separate discrete steps. This merging approach reduces fabrication complexity while achieving the desired segmented structure for improved reliability.

Inventive Principle:
Principle #5Merging (Combining)

3Object-generated harmful factors

If the tunnel barrier layer is divided into multiple portions overlapping with multiple resistance variable elements, then leakage current is blocked more effectively, but the device structure becomes more complex

Engineering Contradiction:
Improveleakage current blockingVSAvoiddevice structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The tunnel barrier layer is segmented into multiple portions, each strategically positioned to overlap with specific resistance variable elements at line intersections. This segmentation creates multiple independent blocking points that effectively prevent leakage current while maintaining a relatively simple overall device structure through the use of standard cross-point memory architecture.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design decreases the operation voltage of memory cells, simplifies fabrication processes, and reduces costs by improving the reliability of the tunnel barrier layer, effectively blocking leakage currents and enhancing data storage characteristics.

Implementation Method 1

The tunnel barrier layer is formed of a dielectric material which has a larger energy band gap than an energy band gap of the resistance variable layer

Methodology Applied
Scientific EffectEnergy band gap: Dielectric

Implementation Method 2

semiconductor devices store data using a characteristic switching between different resistance states according to a voltage or current applied thereto

Methodology Applied
Scientific EffectResistive switching: Electrical Resistance

Data Source

PatentUS9455401B2Memory device having a tunnel barrier layer in a memory cell, and electronic device including the same
Publication Date: 2016.09.27 SK HYNIX INC
  • US9455401B2 patent drawing
  • US9455401B2 patent drawing
  • US9455401B2 patent drawing

AI summary

An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, a resistance variable layer interposed between the first lines and the second lines, a tunnel barrier layer interposed between the resistance variable layer and the first lines, and an intermediate electrode layer interposed between the resistance variable layer and the tunnel barrier layer. The tunnel barrier layer and the intermediate electrode layer overlap with at least two neighboring intersection regions of the first lines and the second lines.