Segmented Variable Resistance Memory for Neural Network Synaptic Weights
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face challenges in efficiently storing and retrieving synaptic weights for neural networks, particularly in achieving reversible short-term and irreversible long-term memory operations with high conductivity and data retention, while maintaining low power consumption and high memory cell density.
Innovation Solution
A memory array with a first portion for short-term memory operations and a second portion for long-term memory operations, utilizing variable resistance memory cells that increase conductivity through pulse control, mimicking biological learning mechanisms by reversible and irreversible degradation mechanisms, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single memory array is used for both short-term and long-term memory operations, then device complexity is reduced, but the ability to perform reversible and irreversible memory operations with high conductivity and data retention is compromised
Solution Approach 1:
The memory array is divided into two distinct portions: a first portion for short-term memory operations and a second portion for long-term memory operations. This segmentation allows each portion to be optimized for its specific function, with the first portion supporting reversible operations and the second portion supporting irreversible operations, thereby resolving the contradiction between device simplicity and operational reliability.
2Quantity of substance
If variable resistance memory cells are used to store synaptic weights, then memory cell density is increased, but power consumption increases due to frequent read/write operations
Solution Approach 1:
By segmenting the memory array into short-term and long-term portions, the system can store frequently accessed synaptic weights in the long-term portion using irreversible operations that consume less power, while the short-term portion handles temporary operations. This reduces overall power consumption while maintaining high memory cell density through the use of variable resistance memory cells.
Solution Approach 2:
The system changes the operational parameters of the variable resistance memory cells by applying different pulse sequences: a first pulse sequence for short-term memory operations and a second pulse sequence for long-term memory operations. This parameter change allows the same hardware to operate in different modes, optimizing power consumption for each operation type while maintaining high density.
3Reliability
If pulse control is used to increase conductivity in memory cells, then synaptic weight storage is improved, but manufacturing precision requirements increase
Solution Approach 1:
The pulse control mechanism is segmented into two distinct control schemes: a first pulse sequence for short-term memory and a second pulse sequence for long-term memory. Each sequence is optimized for its specific purpose, with the second sequence designed to be more tolerant to manufacturing variations. This segmentation reduces the overall manufacturing precision requirements while improving synaptic weight storage reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient storage and retrieval of synaptic weights with increased conductivity for both short-term and long-term memory operations, improving memory cell density and data retention while reducing power consumption.
Implementation Method 1
A memory array with a first portion for short-term memory operations and a second portion for long-term memory operations, utilizing variable resistance memory cells that increase conductivity through pulse control
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.