Segmented Vertical Channel Transistors for Higher 3D Circuit Density
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in achieving high-density 3D circuit designs due to limitations in scaling transistors beyond single-digit nanometer nodes, making it difficult to increase transistor density in volume rather than area.
Innovation Solution
The method involves forming vertical channel field effect transistors by segmenting vertical channels into multiple channels, using 3D vertical segmentation of silicon transistor regions to increase circuit density, and applying these segmented transistors to any 3D vertical design for enhanced layout density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional 2D planar transistor fabrication is used, then manufacturing process is simpler and well-established, but transistor density per unit area cannot be further increased at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from 2D planar transistor fabrication to 3D vertical transistor stacking by forming vertical channel structures that extend perpendicular to the substrate surface. Multiple transistor layers are stacked vertically, with each layer containing source, drain, and gate regions arranged in three dimensions. This dimensional transition enables continued scaling and increased transistor density per unit area at single-digit nanometer nodes.
Solution Approach 2:
The patent segments the vertical channel structure into multiple discrete transistor layers stacked on top of each other. Each transistor layer is formed as a separate segment with its own source, drain, and gate regions. The vertical channel is divided into multiple segments along the vertical axis, allowing independent control and electrical connection of each transistor layer through conductive interconnects.
2Manufacturing precision
If 3D vertical transistor stacking is implemented, then transistor density per unit area increases, but manufacturing process complexity increases significantly
Solution Approach 1:
The patent performs preliminary actions by first forming the vertical channel structure and sacrificial layers before creating the gate and source/drain regions. The sacrificial layers are deposited and patterned in advance to define the vertical channel geometry. This preliminary structuring simplifies subsequent steps for forming the stacked transistor layers, as the vertical channels are already in place to guide the formation of gates and contacts.
Solution Approach 2:
The patent uses sacrificial layers as intermediary structures during fabrication. These sacrificial layers are deposited between the substrate and the vertical channel structures, and between vertical channel layers, to define and protect the vertical channel geometry during processing. The sacrificial layers are later removed to create the final vertical channel structures, having served their intermediary purpose during the fabrication sequence.
3Quantity of substance
If vertical channels are segmented into multiple channels, then circuit density increases by 2 times to N times per transistor level, but manufacturing process steps increase
Solution Approach 1:
The patent merges multiple transistor layers into a single integrated vertical stack structure. Multiple source, drain, and gate regions are combined in the vertical dimension to form a compact stacked transistor assembly. This merging approach increases the number of transistors per unit area by stacking N layers vertically, achieving 2 times to N times density improvement while maintaining a compact footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively doubles or multiplies circuit density per transistor level, depending on the number of divisions, while reducing production costs, and can be applied to various 3D vertical transistor designs.
Implementation Method 1
Vertical channel structures are formed extending through the openings of the layer stack, the vertical channel structures formed by epitaxial growth
Data Source
AI summary
A method of microfabrication includes forming an initial vertical channel structure of semiconductor material protruding from a surface of a substrate such that the initial vertical channel structure has a current flow path that is perpendicular to the surface of the substrate. The initial vertical channel structure is segmented lengthwise into a plurality of independent vertical channel structure segments, each vertical channel structure segment having a respective current flow path that is perpendicular to the surface of the substrate.