Segmented Via Plating for Circuit Board Heat Dissipation

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Solution Overview

Problem

Conventional large-area vias on circuit boards face challenges in stable plating of large-diameter via holes, leading to dimple regions and reduced reliability, especially when trying to improve heat dissipation and shielding characteristics.

Innovation Solution

The proposed circuit board design features a via structure with multiple via parts in a multi-layered structure within the via hole, where the first via part is disposed in an outer region and the second via part is in a central region, each with distinct surface roughness and protrusions, allowing for stable and uniform plating.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a large-diameter via hole is used to improve heat dissipation and shielding characteristics, then heat dissipation performance is improved, but plating stability deteriorates due to dimple region formation

Engineering Contradiction:
Improveheat dissipation performanceVSAvoidplating stability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The via hole is divided into multiple regions (first region and second region) with different plating thicknesses. The first region has a greater plating thickness than the second region, creating a stepped plating structure that prevents dimple formation while maintaining large via hole diameter for heat dissipation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the via hole are given different plating characteristics. The first region (typically the upper or lower region) receives thicker plating while the second region receives thinner plating, optimizing both plating stability and heat dissipation performance in different locations.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If the via hole diameter is increased to break design constraints, then design freedom is improved, but manufacturing precision deteriorates due to plating uniformity issues

Engineering Contradiction:
Improvedesign freedomVSAvoidvia plating uniformity
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The via hole plating is segmented into multiple regions with different thicknesses, allowing large via hole diameters to be manufactured with controlled precision by addressing different regions with appropriate plating thicknesses.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The plating thickness parameter is varied across different regions of the via hole. By changing the plating thickness from the first region to the second region, the invention achieves both large via hole dimensions and controlled manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enables stable plating of large-diameter via holes, improves the uniformity of via plating, enhances heat dissipation performance, and increases design freedom by breaking constraints on via hole size and thickness ratios.

Implementation Method 1

a first via part disposed in a first region of the first via hole; and a second via part disposed in a second region other than the first region of the first via hole... the first surface has a first surface roughness; and wherein the second surface has a second surface roughness different from the first surface roughness

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS20250071897A1Circuit board
Publication Date: 2025.02.27 LG INNOTEK CO LTD
  • US20250071897A1 patent drawing
  • US20250071897A1 patent drawing
  • US20250071897A1 patent drawing

AI summary

A circuit board according to an embodiment includes an insulating layer including a first via hole; a first via disposed in the first via hole of the insulating layer; wherein the first via includes: a first via part disposed in a first region of the first via hole; and a second via part disposed in a second region other than the first region of the first via hole; wherein the second region is a central region of the first via hole, and the first region is an outer region surrounding the second region; wherein the first via part and the second via part includes: a first surface in contact with each other; and a second surface other than the first surface exposed on the insulating layer; wherein the first surface has a first surface roughness; wherein the second surface has a second surface roughness different from the first surface roughness.