Segmented VSS Lines for SRAM Read-Write Margin Improvement
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Solution Overview
Problem
Reduced operation voltages in integrated circuits lead to decreased read and write margins in SRAM cells, causing errors due to static noise, and existing solutions that provide dynamic power voltages for improved margins result in performance compromise and complex circuit designs.
Innovation Solution
The implementation of a power circuit that provides different VSS voltages to SRAM cells within an array, with each column connected to a separate VSS line, allowing for variable voltages to be applied during read and write operations, improving margins without the need for complex dynamic power circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If operation voltage is reduced to scale integrated circuits, then power consumption is reduced, but read and write margins are reduced causing errors due to static noise
Solution Approach 1:
The VSS lines are segmented into multiple independent lines (first VSS line, second VSS line, etc.), with each line serving a specific column of SRAM cells. This segmentation allows independent voltage control for different column groups, enabling improved read and write margins through selective voltage adjustment without affecting the entire array, thus resolving the contradiction between low power consumption and reliable operation.
Solution Approach 2:
Different VSS voltages are applied to different column groups locally. The power circuit provides different VSS voltages to different VSS lines, allowing local optimization of read and write margins in specific column regions while maintaining lower voltages in other regions, thereby improving reliability without proportionally increasing power consumption across the entire array.
2Reliability
If dynamic power voltages are provided to improve read and write margins, then reliability is improved, but device complexity and chip space increase
Solution Approach 1:
Instead of implementing complex dynamic voltage switching circuits for the entire array, the patent segments the VSS lines into multiple independent lines. This simpler segmentation approach allows margin improvement through basic voltage selection rather than complex dynamic switching, reducing circuit complexity while maintaining reliability benefits.
Solution Approach 2:
Rather than dynamically adjusting VDD (power supply voltage) as in conventional approaches, this patent adjusts VSS (ground voltage) instead. By inverting the control approach from VDD modulation to VSS modulation, the patent achieves margin improvement with simpler circuitry, as VSS line control is more straightforward than dynamic VDD generation.
3Reliability
If dynamic power voltages are provided to improve read and write margins, then reliability is improved, but productivity decreases due to performance compromise
Solution Approach 1:
The patent implements dynamic voltage selection capability through segmented VSS lines, where different VSS voltages can be applied to different column groups based on operation type (read or write). This dynamic adaptability allows the array to optimize performance for specific operations without the overhead of complex dynamic power circuits, maintaining productivity while improving reliability.
Data Source
AI summary
An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.