Segmented Wall Structure for Stacked Gate Cell Isolation
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Solution Overview
Problem
As semiconductor devices become increasingly integrated, there is a need to enhance the reliability of memory cells while reducing their dimensions to improve device performance and lower production costs.
Innovation Solution
A non-volatile memory device is manufactured with a non-continuous wall structure surrounding a stacked gate structure, utilizing a conductive layer between segmented portions of the wall structure to maintain uniform thickness and prevent re-flow of materials during etching, thereby protecting the active area and avoiding cell bridging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If continuous wall structure is used surrounding stacked gate structure, then manufacturing process is simpler, but material re-flow during etching causes non-uniform thickness and cell bridging
Solution Approach 1:
The continuous wall structure is divided into segmented portions with conductive layers positioned between them. This segmentation prevents material re-flow during etching while maintaining structural support, resolving the contradiction between manufacturing simplicity and thickness uniformity.
Solution Approach 2:
Conductive layers are introduced as intermediary elements between wall portions. These layers act as barriers that prevent material re-flow during etching processes, ensuring uniform wall thickness while allowing the overall structure to be manufactured using standard processes.
2Device complexity
If wall structure without conductive layers is used, then device structure is simpler, but active area protection is insufficient leading to cell bridging
Solution Approach 1:
Conductive layers serve as intermediary barrier layers between wall portions, preventing material re-flow that would compromise active area protection. This maintains cell isolation integrity while adding minimal structural complexity.
Solution Approach 2:
Conductive layers are positioned in advance between wall portions before etching occurs, preemptively preventing material re-flow and protecting the active area from cell bridging issues.
3Productivity
If dimensions of memory devices are reduced for higher integration, then device density increases, but reliability of memory cells decreases
Solution Approach 1:
The wall structure is segmented with conductive layers that prevent material re-flow, maintaining precise dimensional control and cell isolation even as overall device dimensions are reduced for higher integration density.
Solution Approach 2:
The conductive layers create physical barriers analogous to hydraulic seals, preventing material 'flow' during etching processes. This maintains manufacturing precision and cell reliability at reduced device dimensions.
Data Source
AI summary
A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.