3D Capacitance Extraction Using Segmented Wire Analysis
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Solution Overview
Problem
Existing integrated circuit design methods struggle to accurately reduce parasitic capacitance, which affects circuit timing and performance, especially in advanced technology nodes like 7 nanometer designs.
Innovation Solution
A method for analyzing and extracting parasitic capacitance in integrated circuits by dividing target wires into segments based on effective spaces of crossing wires, using a parameterized function to determine these spaces, and applying capacitance analysis to each segment to accumulate total capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional parasitic capacitance extraction methods are used, then the extraction process is simple and fast, but the accuracy of capacitance extraction is insufficient, especially in advanced technology nodes
Solution Approach 1:
The target wire is divided into multiple segments based on the effective spaces of crossing wires. Each segment is analyzed separately using capacitance analysis, and the results are accumulated to obtain the total capacitance. This segmentation approach improves accuracy by capturing local variations in capacitance that would be missed in a conventional uniform analysis.
Solution Approach 2:
Different capacitance analysis methods are applied to different segments of the target wire based on their local characteristics. The effective space of each crossing wire determines how the target wire is segmented, allowing localized accurate capacitance extraction where needed while maintaining efficiency elsewhere.
2Measurement precision
If the target wire is divided into more segments for accurate capacitance extraction, then the extraction accuracy improves, but the computational complexity and time increase
Solution Approach 1:
The effective spaces of crossing wires are determined beforehand using a parameterized function with fitted parameters. This preliminary determination of effective spaces allows the target wire to be segmented in advance based on these pre-computed values, avoiding repeated complex calculations during the actual capacitance extraction process.
Solution Approach 2:
A parameterized function with adjustable parameters is used to model the effective space of crossing wires. By fitting these parameters to match actual wiring patterns, the model achieves high accuracy while maintaining computational efficiency, as the fitted parameters can be quickly applied without requiring full 3D field calculations.
3Measurement precision
If a parameterized function with fitted parameters is used to determine effective spaces, then the accuracy of capacitance extraction improves, but the complexity of the analysis method increases
Solution Approach 1:
Instead of performing complex 3D field calculations for every wiring configuration, a parameterized function is created that copies the essential characteristics of the effective space behavior. The function parameters are fitted to match reference data from accurate 3D calculations, allowing the simplified function to reproduce accurate results without the computational burden of full 3D analysis.
Data Source
AI summary
A method for analyzing an area of a target wire includes determining a wiring pattern for performing pattern-based 3D capacitance extraction, determining the target wire included in the wiring pattern, and dividing the target wire into segments based on effective spaces of various crossing wires. The method further includes determining a capacitance analysis that applies for each of the segments, determining a plurality of capacitance results corresponding to the capacitance analysis applied to each of the segments, and accumulating the plurality of capacitance results to extract a total capacitance corresponding to the target wire. The segments are based on an effective spacing of crossing wires, which are located above the target wire and extend across the target wire. The effective spaces are determined using a parameterized function that implements at least two adjustable parameters that are set to obtain the wiring pattern using a fitting process.