Segmented Memory Word Line Decoders for Voltage Drop Reduction
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Solution Overview
Problem
Conventional memory systems face significant voltage drops along selected word lines due to capacitive and/or leakage current, leading to varying voltage conditions for memory cells, which requires higher current support or increased supply voltage when activating multiple memory cells during read and write operations.
Innovation Solution
The proposed solution involves segmenting word lines and using multiple word line decoders, as well as selectively controlling sub-blocks within memory blocks via switches to reduce the number of activated memory cells, thereby minimizing voltage drops by distributing memory cell activation across multiple sub-blocks and blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory cells are activated during read and write operations, then productivity is improved, but voltage drop increases due to capacitive and leakage current
Solution Approach 1:
The memory array is divided into multiple sub-blocks, each with its own dedicated word line decoder. This segmentation allows the system to activate only the specific sub-block containing the target memory cell, rather than activating multiple sub-blocks simultaneously. The segmentation of the decoder into multiple independent units (first decoder, second decoder, etc.) enables selective activation of individual sub-blocks, reducing the total number of activated cells and thereby reducing voltage drop while maintaining fast access to individual cells.
2Reliability
If higher current is supplied to word lines, then voltage stability is improved, but power consumption increases
Solution Approach 1:
The word line decoding function is segmented into multiple independent decoders, each serving a specific sub-block. This allows the system to activate only the decoder and corresponding word line for the specific sub-block containing the target memory cell. By activating only one decoder at a time instead of multiple decoders simultaneously, the system maintains stable voltage on the activated word line while significantly reducing total power consumption, as only a fraction of the total decoder circuitry is active during each operation.
3Loss of energy
If the number of activated memory cells is reduced, then voltage drop is minimized, but access time increases
Solution Approach 1:
The memory system is segmented into multiple sub-blocks with dedicated decoders, enabling parallel access capability. When a memory cell needs to be accessed, the system activates only the specific sub-block containing that cell, reducing voltage drop. The segmentation allows the system to maintain fast access times because each decoder is optimized for quick activation of its assigned sub-block, and the reduced number of activated cells within that sub-block ensures minimal voltage drop while maintaining speed.
4Manufacturing precision
If multiple word line decoders are used, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The decoder functionality is segmented into multiple independent units, each responsible for a specific sub-block of the memory array. This segmentation improves manufacturing precision because each decoder can be independently designed and tested, ensuring accurate selection of memory cells within its assigned sub-block. The modular nature of the segmentation means that while the overall system has multiple decoders, each individual decoder unit is simpler and easier to manufacture with high precision, and the regular repeating pattern of the segmentation facilitates standardized manufacturing processes.
Data Source
AI summary
A memory system includes a memory array and a read/write module. The memory array includes bit lines, word lines, and memory cells. Each of the memory cells is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory cells include a first memory cell and a second memory cell. The first memory cell is located at the intersection of a first bit line of the bit lines and a first word line of the word lines. The second memory cell is located at the intersection of a second bit line of the bit lines and a second word line of the word lines. The read/write module is configured to concurrently activate the first memory cell and the second memory cell to simultaneously access both the first memory cell and the second memory cell.