Segmented Word Line Flash Memory Thermal Annealing
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Solution Overview
Problem
Flash memory technologies face challenges in improving the speed of operation and endurance due to damage accumulation during program and erase cycling, which existing technologies have not effectively addressed.
Innovation Solution
The implementation of thermally annealing flash memory cells during read, program, and erase operations using resistive heating generated by current flow in word lines to repair damage and enhance charge trapping structures, thereby improving endurance and erase speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If conventional flash memory program and erase operations are performed repeatedly, then memory operation count increases, but damage accumulates in charge trapping structures reducing endurance
Solution Approach 1:
The patent applies periodic thermal annealing operations during or between program/erase cycles to repair damage in charge trapping structures. By periodically heating the memory cell to elevated temperatures (e.g., 150-400°C) for short durations, the annealing process restores trapped charge and repairs interface damage, enabling the memory to withstand over 1 million program/erase cycles while maintaining reliable operation
Solution Approach 2:
The patent changes the temperature parameter of the memory cell by applying thermal energy during annealing operations. By temporarily elevating the cell temperature to a specific range (150-400°C) and then returning it to normal operating temperature, the patent activates repair mechanisms that restore charge trapping capability without permanently altering the memory structure, thereby improving endurance while maintaining operational reliability
2Speed
If conventional erase operations are performed, then memory cells are erased, but erase speed is limited by electron de-trapping time
Solution Approach 1:
The patent utilizes a phase transition in the thermal state of the memory cell to accelerate erase operations. By heating the cell to elevated temperatures during the erase process, electrons gain thermal energy that assists their escape from trapped states. This thermal phase transition reduces the de-trapping time constant, enabling faster erase speeds while maintaining complete erasure of the memory cell
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances the endurance of flash memory devices to over 1 million cycles and improves erase speed by thermally annealing charge trapping structures, maintaining performance over extended cycling.
Implementation Method 1
resistive heating generated by current flow in word lines
Implementation Method 2
thermally annealing charge trapping structures in the memory cells
Data Source
AI summary
A memory includes an array of memory cells including rows and columns including segmented word lines along the rows. The segments of the segmented word lines include local word lines. First and second switches are coupled to corresponding first and second ends of local word lines. The memory includes circuitry coupled to the first and second switches to connect bias voltages to the local word lines to induce current flow for thermal anneal. The circuitry includes pairs of global word lines along corresponding rows. The pairs of global word lines include first global word lines coupled to the first switches in the local word lines along the corresponding rows, and second global word lines coupled to the second switches in the local word lines along the corresponding rows. The memory includes bit lines along corresponding columns. Bit lines can comprise local bit lines coupled to global bit lines.