Segregated Dual-Core FPGA Layout for Dissimilar Flight Control

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Solution Overview

Problem

Designing aircraft control systems that meet stringent safety requirements for dissimilarity in processing cores while minimizing component count and complexity is challenging, as existing solutions often require multiple, physically separate FPGAs or shared peripheral components, which can be costly and inefficient.

Innovation Solution

A dual-core FPGA architecture where each processing circuit has its own unique numerical core and peripheral components, segregated on the same substrate, with external communication lines to ensure dissimilarity and redundancy, allowing for independent operation and reduced component count.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple physically separate FPGAs are used to ensure dissimilarity of processing cores, then reliability and safety requirements are met, but device complexity and component count increase

Engineering Contradiction:
Improvesafety of aircraft control systemVSAvoidcomponent count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple dissimilar processing circuits onto a single FPGA substrate, integrating what would traditionally require separate physical devices. This consolidation maintains the dissimilarity requirement for safety while reducing the overall component count and system complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The FPGA substrate is segmented into distinct processing circuits with separate logical blocks, each implementing different functionality. This segmentation ensures that each circuit remains dissimilar while sharing the same physical platform, satisfying both safety requirements and complexity reduction goals.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If processing circuits share peripheral components on the same FPGA, then component count is reduced, but dissimilarity requirements cannot be satisfied

Engineering Contradiction:
Improvecomponent countVSAvoiddissimilarity of processing cores
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the FPGA resource allocation such that each processing circuit is assigned dedicated logical blocks and peripheral components. This segmentation prevents sharing that would compromise dissimilarity while maintaining reasonable component utilization on the single substrate.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions or logical blocks of the FPGA are assigned different qualities and functions tailored to each processing circuit's specific requirements. This local differentiation ensures each circuit maintains its unique characteristics while operating on the same physical platform.

Inventive Principle:
Principle #3Local quality

3Reliability

If dissimilar processing circuits are implemented on the same FPGA with segregated architecture, then dissimilarity is ensured, but inter-core communication becomes more complex

Engineering Contradiction:
Improvedissimilarity of processing coresVSAvoidcommunication architecture
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces intermediary communication interfaces and protocols that facilitate interaction between the dissimilar processing circuits. These intermediaries provide standardized communication pathways that simplify the complexity of direct inter-core communication while maintaining the required dissimilarity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3764235B1Field programmable gate array (FPGA) having dissimilar cores
Publication Date: 2022.10.26 RATIER FIGEAC SAS
  • EP3764235B1 patent drawingFigure 1
  • EP3764235B1 patent drawingFigure 2~3
  • EP3764235B1 patent drawingFigure 4

AI summary

A field programmable gate array (FPGA) (10) having at least first (12) and second (14) processing circuits implemented thereon. Each of the first and second processing circuits comprises a numerical core (121, 141) and associated peripheral components. The numerical core (121) in the first processing circuit is dissimilar to the numerical core (141) in the second processing circuit. The first and second processing circuits (12, 14) are segregated from each other in floorplan view.