SEL Mitigation Detect and Unlatch Circuitry
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Solution Overview
Problem
Integrated circuits face the challenge of single event latch-up (SEL), which leads to abnormal high-current states caused by energetic particles, resulting in device functionality loss and potential damage, with conventional methods requiring power removal to mitigate, causing loss of functionality and memory states.
Innovation Solution
An integrated circuit (IC) chip with integrated circuitry for detecting and mitigating SEL events, featuring a current limiting circuit and latch sensing circuit that allows for unlatching of latched silicon controlled rectifier (SCR) devices without reducing supply voltage, enabling local mitigation and maintaining functionality of other circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is removed from the IC die to reduce voltage across the SCR structure, then the latch-up can be sustained no longer and high current disappears, but the IC die loses functionality and memory states are lost
Solution Approach 1:
The patent divides the IC die into multiple power domains with separate power rails. When an SEL event is detected in one domain, only the power to that specific domain is reduced, while other domains continue to receive full power and maintain functionality. This segmentation allows localized SEL mitigation without system-wide functional loss.
Solution Approach 2:
The patent implements local SEL mitigation by applying voltage reduction only to the specific circuit region experiencing the latch-up event. The current limiting circuit is activated selectively in the affected domain, while other parts of the IC die operate normally with full power, preserving overall system functionality.
2Object-affected harmful factors
If voltage across the SCR structure is reduced to mitigate latch-up, then high current conduction stops, but power removal causes system downtime and memory loss
Solution Approach 1:
The patent segments the power supply into multiple independent rails, allowing the voltage reduction to be applied only to the specific rail affected by SEL. This enables rapid mitigation of high current conduction in the affected domain without causing system-wide downtime or memory loss in other domains.
Solution Approach 2:
The patent detects SEL events early through monitoring circuits that sense abnormal current conditions. Upon detection, the current limiting circuit is immediately activated to reduce voltage across the SCR structure, stopping high current conduction before it causes damage. This preliminary detection and rapid response minimize system downtime.
3Reliability
If conventional power removal method is used to unlatch transistors, then the latch-up condition is resolved, but other circuits on the die cannot maintain operation
Solution Approach 1:
The patent implements multiple independent power rails that allow selective voltage reduction to the affected circuit domain while maintaining power supply to other circuits. This enables latch-up resolution in the specific domain experiencing SEL events while other circuits continue to operate normally, maintaining overall system adaptability and versatility.
Solution Approach 2:
The patent applies voltage reduction locally only to the circuit region experiencing latch-up, while other regions maintain full operating voltage. This local mitigation approach resolves the latch-up condition in the affected area without impacting the operation of other circuits, preserving system functionality and adaptability.
Data Source
AI summary
An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.