Select Device Structure for Resistive Memory Read Disturbance
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Solution Overview
Problem
Resistive memory arrays face read disturbance issues due to current flow into unselected word lines during read operations, which reduces the ability to distinguish between data states and increases power dissipation and noise.
Innovation Solution
A select device structure comprising a two-terminal select device in series with a non-ohmic device, providing a composite current-voltage profile that enhances the on/off current ratio and acts as a current limiter, allowing high voltage bipolar programming without current flow into unselected word lines during lower voltage read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current flows through selected memory cell during read operation, then data state can be sensed, but current also flows into unselected word lines causing read disturbance
Solution Approach 1:
The patent introduces a select device as an intermediary component between the memory cell and the access lines. This select device acts as a mediator that controls current flow direction and magnitude, allowing current to pass through the selected memory cell for sensing while blocking or limiting current flow into unselected word lines, thereby preventing read disturbance
Solution Approach 2:
The select device provides different electrical characteristics to different regions of the memory array. At the selected memory cell location, the select device allows high current flow for proper sensing, while at unselected word line locations, it maintains low current flow to prevent disturbance. This spatial variation in electrical properties resolves the contradiction between sensing capability and read disturbance
2Speed
If high current is used for programming memory cell, then programming speed improves, but power dissipation and noise increase
Solution Approach 1:
The patent segments the current path into distinct controlled sections using select devices. During programming operations, the select device is configured to allow high current flow through the selected memory cell for fast programming, while during read operations, it limits current flow to reduce power dissipation and noise. This temporal segmentation of current characteristics resolves the contradiction between programming speed and power consumption
3Device complexity
If simple select device is used, then device complexity is reduced, but ability to limit current and prevent read disturbance is insufficient
Solution Approach 1:
The patent employs a composite select device structure combining multiple functional layers or materials with different electrical properties. This composite structure provides superior current limiting capability and selectivity compared to simple single-material devices, while maintaining reasonable fabrication complexity. The composite nature allows simultaneous achievement of current limiting function and acceptable device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces leakage and disturb effects in partially selected resistive memory cells, improving signal-to-noise ratio and power efficiency by maintaining a high on/off current ratio and supporting 3D stacking of memory arrays.
Implementation Method 1
A select device structure comprising a two-terminal select device in series with a non-ohmic device, providing a composite current-voltage profile
Data Source
AI summary
Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the two terminal select device. The combined two terminal select device and non-ohmic device provide a composite I-V profile of the select device structure that includes a modified characteristic as compared to the I-V profile, and the modified characteristic is based on at least one operating voltage associated with the memory cell.