Select Gate Adaptive Bias for Uniform Memory Erase Thresholds
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Solution Overview
Problem
Due to process variations during manufacturing, non-volatile memory cells erase to different threshold voltage ranges, leading to non-uniform and potentially erroneous data storage and retrieval.
Innovation Solution
Implementing drain-side and source-side select gate transistors with adjustable voltages based on pre-read threshold voltages to ensure uniform erased threshold voltage distributions during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional erase operations are used without adaptive bias adjustment, then the erase operation is simple and fast, but the erased threshold voltage distribution becomes non-uniform and erroneous
Solution Approach 1:
The patent performs preliminary actions by pre-reading the threshold voltages of select gate transistors before the erase operation and determining which transistors require bias adjustment. This advance preparation enables the subsequent adaptive bias adjustment during erase to achieve uniform erased threshold voltage distributions without excessive complexity.
Solution Approach 2:
The patent dynamically changes the bias parameters (voltages) applied to select gate transistors during the erase operation based on their pre-read threshold voltage characteristics. By adjusting the gate voltages adaptively, the system compensates for process variations and achieves uniform erased threshold voltage distributions across all memory cells.
2Reliability
If adaptive bias adjustment is implemented during erase operations, then uniform erased threshold voltage distributions are achieved, but additional read operations and voltage adjustments are required
Solution Approach 1:
The patent performs the threshold voltage read and analysis operations before the actual erase operation, preparing the necessary information in advance. This preliminary action allows the erase operation to proceed efficiently with pre-determined bias adjustments, minimizing the time penalty.
Solution Approach 2:
The system uses its own read capability to characterize the select gate transistors and determine the appropriate bias adjustments needed. This self-characterization approach eliminates the need for external calibration or manual adjustment, enabling the system to automatically optimize its erase operation for maximum reliability.
3Manufacturing precision
If fixed bias voltages are applied to select gate transistors, then the erase operation is simple to implement, but process variations cause non-uniform erased threshold voltage distributions
Solution Approach 1:
The patent changes the bias parameters dynamically based on measured transistor characteristics rather than using fixed values. By adjusting the gate voltages according to pre-read threshold voltages, the system compensates for manufacturing process variations and achieves uniform erased threshold voltage distributions.
Solution Approach 2:
The patent implements a feedback mechanism where the threshold voltages of select gate transistors are read and used to determine the appropriate bias adjustments for the erase operation. This feedback loop enables the system to adapt to process variations and maintain uniform erased threshold voltage distributions across different manufacturing batches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability and accuracy of data storage by maintaining tight and uniform erased threshold voltage distributions, reducing errors in programming and reading operations.
Implementation Method 1
A control means is configured to pre-read the drain-side transistor threshold voltage of the drain-side select gate transistors and the source-side transistor threshold voltage of source-side select gate transistors
Implementation Method 2
The control means is also configured to adjust at least one of a drain-side select gate voltage applied to the drain-side select gate transistors and a source-side select gate voltage applied to the source-side select gate transistors
Data Source
AI summary
A memory apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a drain-side transistor threshold voltage. The memory apparatus also includes source-side select gate transistors for coupling to a source-side of each of the memory holes and configured to retain a source-side transistor threshold voltage. A control means pre-reads the drain-side transistor threshold voltage of the drain-side select gate transistors and the source-side transistor threshold voltage of source-side select gate transistors of the memory holes having the memory cells being erased in an erase operation. The control means adjusts at least one of a drain-side select gate voltage applied to the drain-side select gate transistors and a source-side select gate voltage applied to the source-side select gate transistors based on at least one of the pre-read of the drain-side transistor threshold voltage and the source-side transistor threshold voltage.