3D Memory Select Gate Electrode Thickness Design
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Solution Overview
Problem
The high resistance of metal lines in three-dimensional memory devices, particularly due to the narrower width of drain select gate electrodes, limits the performance of memory cells within these devices.
Innovation Solution
A three-dimensional memory device design where the drain select gate electrode has a greater effective thickness than the word lines, and a method of forming this structure by creating an alternating stack of insulating and spacer material layers over a substrate, forming memory stack structures, and selectively removing spacer material layers to create backside recesses for the drain select gate electrode and word lines, ensuring the drain select gate electrode is thicker.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the drain select gate electrode is made narrower to fit within the memory structure, then the device density is improved, but the resistance of the drain select gate electrode increases
Solution Approach 1:
The patent increases the thickness (vertical dimension) of the drain select gate electrode to compensate for the reduced width (horizontal dimension). This dimensional transition allows the electrode to maintain adequate conductivity while fitting within the constrained memory structure, thereby resolving the contradiction between device density and electrode resistance.
Solution Approach 2:
The patent changes the geometric parameters of the drain select gate electrode by increasing its thickness while decreasing its width. This parameter adjustment optimizes the balance between maintaining low resistance and achieving high device density, directly addressing the technical contradiction.
2Reliability
If the drain select gate electrode is made thicker to reduce resistance, then the conductivity is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent forms the drain select gate electrode with greater thickness during the initial electrode formation process, before subsequent patterning and etching steps. This preliminary action ensures the electrode has adequate conductivity from the start, and the thicker profile is maintained through the manufacturing process, reducing the need for additional complex manufacturing steps.
Solution Approach 2:
The patent creates an asymmetric electrode profile where the drain select gate electrode has different dimensions compared to word lines - specifically thicker but narrower. This asymmetric design optimizes conductivity for the drain select gate while maintaining appropriate dimensions for other components, managing manufacturing complexity through targeted dimensional differentiation.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.