Flash Memory Select Gate Etch-Back for Smaller Access Transistors
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Solution Overview
Problem
Traditional semiconductor manufacturing methods face limitations in shrinking the minimum gate length of access transistors due to feature mismatches and the need for thick photoresistors, which hinder the reduction of space between polysilicon layers in flash memory cells.
Innovation Solution
A manufacturing method that involves forming stacked gates with a floating gate and a control gate, using an etch-back process to create symmetric select gates without a mask, allowing for simultaneous formation of transistors and reducing the height of select gates relative to control gates, enabling easier shrinking of access transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a mask is used when forming an access transistor to prevent cell leakage, then cell leakage is prevented, but feature differences between left and right cells occur, limiting the minimum gate length of access transistors
Solution Approach 1:
The patent extracts and removes the mask formation step from the access transistor fabrication process. By eliminating the mask and using direct etching methods, the invention prevents feature differences between left and right cells while maintaining cell leakage prevention through alternative structural designs in the memory cell architecture
Solution Approach 2:
The patent applies asymmetry by intentionally designing different structures for left and right access transistors. Instead of requiring symmetric features, the invention uses asymmetric contact hole positions and different etching conditions to achieve identical electrical characteristics, thereby resolving the feature matching problem caused by traditional symmetric mask-based fabrication
2Manufacturing precision
If a thick photo resistor is used for etching floating gate polysilicon, ONO layer, and control gate polysilicon, then etching precision is improved, but the space between polysilicon layers of the floating gate cannot be shrunk
Solution Approach 1:
The patent segments the etching process into multiple distinct steps, each targeting specific layers with dedicated etching conditions. Instead of using a single thick photo resistor for all etching operations, the invention employs sequential etching processes with different masks and parameters, enabling precise control of each layer's thickness and spacing, thereby reducing the space between polysilicon layers while maintaining etching precision
Solution Approach 2:
The patent transitions from a single-dimensional thick photo resistor approach to a multi-dimensional process control strategy. By introducing multiple etching steps with varying parameters (temperature, pressure, gas composition, power), the invention achieves precise three-dimensional control over layer spacing and thickness, enabling space reduction between polysilicon layers while preserving etching accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the symmetric formation of gate polysilicon in access transistors, facilitating the shrinking of access transistors and ensuring identical electrical performance, thus overcoming the limitations of traditional methods.
Implementation Method 1
forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate
Implementation Method 2
forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate
Data Source
AI summary
A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate.