Select Gate Integrity Checks for Non-Volatile Memory Data Security
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Solution Overview
Problem
Memory sub-systems face data loss due to current leakage from defective select gates in non-volatile memory devices, particularly during sanitize operations, leading to unreliable data storage and retrieval.
Innovation Solution
Implementing a memory sub-system controller that performs select gate integrity checks to identify and invalidate defective blocks by applying voltage pulses to wordlines, thereby preventing current leakage and ensuring reliable data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sanitize operations are performed on memory blocks, then data security is improved, but current leakage from defective select gates causes data loss
Solution Approach 1:
The system performs select gate integrity checks before executing sanitize operations to identify blocks with defective select gates that would cause current leakage. By detecting these defective blocks in advance and excluding them from sanitize operations, the system prevents data loss while maintaining data security for valid blocks.
Solution Approach 2:
The patent introduces an intermediate verification step (select gate integrity check) between the sanitize command and the actual erase operation. This intermediary check acts as a filter to identify and isolate defective blocks, allowing the sanitize operation to proceed safely on valid blocks without causing data loss through current leakage.
2Reliability
If memory sub-system performs erase operations, then data storage reliability is improved, but current leakage from defective select gates undermines this reliability
Solution Approach 1:
The system performs select gate integrity checks before erase operations to identify blocks with defective select gates. By detecting potential current leakage paths in advance, the system can exclude these defective blocks from erase operations, thereby maintaining data storage reliability and preventing the harmful effects of current leakage.
Solution Approach 2:
The patent applies a preliminary anti-action by identifying and isolating defective select gates before they can cause harmful current leakage during erase operations. The integrity check mechanism proactively counteracts the potential harmful effect by preventing the erase operation from being applied to blocks with defective select gates.
3Loss of information
If select gate integrity checks are implemented, then data loss is reduced, but device complexity increases
Solution Approach 1:
The memory sub-system performs self-diagnosis through select gate integrity checks, automatically identifying blocks with defective select gates. This self-service mechanism enables the system to detect and isolate potential data loss risks without requiring external intervention, reducing data loss while the complexity is confined to the control logic within the existing memory controller.
Solution Approach 2:
The select gate integrity check mechanism serves multiple functions: it identifies defective blocks, prevents current leakage, and protects data integrity. By consolidating these functions into a single verification process, the patent reduces data loss without proportionally increasing device complexity, as the same control structure handles multiple protective tasks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces data loss by identifying and invalidating defective blocks, enhancing the performance and reliability of memory sub-systems by minimizing current leakage during erase operations.
Implementation Method 1
applying voltage pulses to wordlines
Data Source
AI summary
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value by measuring a voltage at a select gate of a block while applying a maximum voltage to a drain select line, responsive to determining that the parameter value satisfies a threshold criterion, concluding that the select gate of the block is defective, and responsive to receiving an enhanced erase command referencing the block, discarding the enhanced erase command.