Select Gate Programming in NAND Flash Memory
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Solution Overview
Problem
In flash memory devices, particularly in NAND architecture, there is a need to inhibit select gate transistors during programming operations to prevent over-programming and ensure proper threshold voltage settings across series strings of memory cells, as common control gates for SGD and SGS transistors can lead to unintended programming of unverified transistors.
Innovation Solution
A method for programming select gate drain (SGD) and source (SGS) transistors involves inhibiting already programmed SGD transistors by biasing bit line circuits with specific voltages, using BIAS and HV PROTECT transistors, and selectively applying programming pulses to unprogrammed transistors, ensuring that only the intended transistors reach the target threshold voltage without over-programming others.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If programming voltage is applied to common control gates of SGD transistors in a memory block, then all SGD transistors receive the programming pulse simultaneously, but this causes over-programming of transistors that have already passed program verify
Solution Approach 1:
The patent segments the programming process by dividing the memory block into verified and unverified transistor groups. Individual control gates for SGD transistors are used to selectively apply programming pulses only to unverified transistors, while verified transistors are excluded through their control gate biasing. This segmentation allows simultaneous programming of multiple transistors without over-programming verified ones, resolving the contradiction between programming speed and threshold voltage precision.
Solution Approach 2:
The patent implements preliminary program verify operations to identify which SGD transistors have achieved the target threshold voltage before completing the programming phase. Based on these verify results, the system prepares individual control gate biasing conditions in advance, ensuring that subsequent programming pulses are applied only to transistors that need further programming. This preliminary action prevents over-programming while maintaining efficient parallel processing.
2Productivity
If programming pulses are applied to SGD control gates to program unverified transistors, then programming progress is made, but adjacent memory cells may suffer from breakdown due to high voltage stress
Solution Approach 1:
The patent applies local quality by implementing different voltage conditions in different regions of the memory block. Specifically, word lines adjacent to SGD transistors receiving programming pulses are biased at lower voltages to protect adjacent memory cells from breakdown, while the SGD control gates themselves receive the full programming voltage. This localized voltage differentiation allows high-throughput programming of SGD transistors while protecting neighboring sensitive structures from voltage-induced damage.
3Device complexity
If common control gates are used for SGD transistors across all series strings, then device complexity is reduced, but select gate transistors cannot be individually inhibited during programming
Solution Approach 1:
The patent segments the control mechanism by transitioning from completely common control gates to a hybrid structure where control gates are common at the block level but can be individually biased through additional control lines. This allows the system to maintain the simplicity of common control gate architecture while introducing the capability for individual transistor inhibition through selective biasing of control gates based on program verify status, thus resolving the contradiction between device complexity and programming control accuracy.
Data Source
AI summary
Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.