Select Gate Maintenance Triggered by Post-Write Read Errors
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Solution Overview
Problem
Current memory devices face performance degradation due to independent post-write read (PWR) and select gate maintenance (SGM) operations, which can lead to unnecessary SGM operations and decreased system performance, as they are triggered by probabilistic methods that may not accurately address select gate transistor threshold voltage shifts.
Innovation Solution
Merging PWR and SGM operations by performing SGM only when PWR determines a high bit error rate, allowing for adaptive threshold adjustments to selectively maintain or retire select gate transistors based on their threshold voltages, thereby reducing unnecessary SGM operations and improving memory system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent post-write read and select gate maintenance operations are performed, then memory device reliability is improved, but system performance deteriorates due to unnecessary operations
Solution Approach 1:
The patent merges the post-write read operation and select gate maintenance operation into a single unified operation. The read operation and select gate threshold voltage check are combined into one atomic operation, eliminating the need for separate independent operations. This reduces the total number of operations performed while maintaining both reliability checks (data integrity via read verification and select gate functionality via threshold voltage checking), thus improving system performance without sacrificing reliability.
2Reliability
If select gate maintenance operations are performed frequently, then select gate transistor threshold voltage shifts are corrected, but the number of unnecessary operations increases
Solution Approach 1:
The patent implements a feedback mechanism where the post-write read operation provides information about actual memory cell read errors, which directly reflects the state of select gate transistor threshold voltages. Instead of performing select gate maintenance operations on a fixed schedule or based on probabilistic models, the system uses the feedback from actual read errors to determine when maintenance is truly needed. This feedback-driven approach ensures maintenance operations are performed only when necessary to correct threshold voltage shifts, eliminating wasted time on unnecessary operations.
3Ease of operation
If probabilistic methods are used to trigger operations, then operation simplicity is maintained, but operational accuracy deteriorates
Solution Approach 1:
The patent enables the memory system to self-diagnose the actual need for select gate maintenance operations through the post-write read operation. Instead of relying on external probabilistic triggers or predetermined schedules, the system uses its own operational data (read errors) to automatically determine when maintenance is required. The post-write read operation serves as a self-check mechanism that provides accurate, real-time information about select gate transistor health, replacing inaccurate probabilistic methods with precise self-measurement while maintaining operational simplicity.
Data Source
AI summary
A method is provided that includes performing a post-write read operation on a block of memory cells that includes a select gate transistor, and based on results of the post-write read operation selectively performing a select gate maintenance operation on the select gate transistor.