Select Gate Scan Scheduling for Memory Threshold Voltage Drift
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Solution Overview
Problem
Existing memory devices face reliability issues due to threshold voltage degradation in select gate devices, leading to improper functioning and potential data loss, as current threshold voltage integrity scans are performed at fixed intervals that do not account for individual device behavior, causing inefficiencies and potential host device timeouts.
Innovation Solution
Implementing adaptive scan frequency for threshold voltage integrity scans based on the number of program/erase cycles and the rate of change in threshold voltage, allowing for tailored scan intervals to maintain select gate devices within target voltage thresholds, thereby preventing improper functioning and data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed interval threshold voltage integrity scans are performed, then device reliability is maintained through regular monitoring, but scan efficiency decreases and host device timeouts increase due to intensive periodic scans
Solution Approach 1:
The patent implements dynamic scan interval adjustment based on actual device behavior. The controller monitors threshold voltage changes and adapts the scan frequency accordingly - increasing scan frequency when degradation is detected and reducing it when the device is stable. This dynamic approach replaces fixed periodic scans with adaptive monitoring that responds to actual device needs, improving both reliability and productivity.
Solution Approach 2:
The system incorporates feedback mechanisms where scan results directly influence future scan scheduling. When threshold voltage degradation exceeds a threshold, the system increases scan frequency; when degradation is within acceptable limits, scan frequency is reduced. This feedback loop ensures reliable monitoring while optimizing scan efficiency based on actual device conditions.
2Reliability
If frequent threshold voltage integrity scans are performed, then device reliability is improved through early detection of degradation, but system performance deteriorates due to intensive scans causing host device timeouts
Solution Approach 1:
The patent implements dynamic scan interval adjustment based on actual device behavior. The controller monitors threshold voltage changes and adapts the scan frequency accordingly - increasing scan frequency when degradation is detected and reducing it when the device is stable. This dynamic approach replaces fixed periodic scans with adaptive monitoring that responds to actual device needs, improving both reliability and productivity.
Solution Approach 2:
The system changes the time parameter of scan operations based on device condition. Instead of using a fixed scan interval, the controller adjusts the scan frequency parameter dynamically - performing scans more frequently when threshold voltage degradation is detected and less frequently when the device operates normally. This parameter adaptation prevents unnecessary scans that cause timeouts while ensuring timely detection of reliability issues.
3Ease of manufacture
If uniform scan intervals are applied to all blocks, then manufacturing simplicity is maintained, but device performance deteriorates due to inability to account for individual device degradation rates
Solution Approach 1:
The patent segments the memory device into multiple blocks, each with independent scan scheduling. Instead of applying a uniform scan interval to the entire device, the controller monitors and manages each block individually based on its specific degradation characteristics. This segmentation allows tailored monitoring strategies for different blocks, improving reliability without significantly complicating the manufacturing process.
Solution Approach 2:
The system implements local quality monitoring where each block receives customized scan frequency based on its individual threshold voltage degradation rate. Blocks showing faster degradation receive more frequent scans, while stable blocks are scanned less frequently. This localized approach optimizes reliability for each specific device region while maintaining overall system efficiency.
Data Source
AI summary
A processing device, operatively coupled with a memory device, determines a number of program/erase cycles performed on a block of the memory device. The processing device determines that the number of program/erase cycles performed on the block satisfies a first threshold criterion, wherein the first threshold criterion corresponds to a frequency interval for performing a threshold voltage integrity scan on the block. The processing device performs a threshold voltage integrity scan on the block to determine an error count associated with a current threshold voltage of at least one select gate device of the block. Responsive to the error count associated with the current threshold voltage of the at least one select gate device satisfying a second threshold criterion, the processing device determines a rate of change associated with the current threshold voltage of the at least one select gate device. The processing device updates, based on the rate of change, the frequency interval for performing a threshold voltage integrity scan on the block.