3D Memory Select Gate Short Circuit Prevention
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Solution Overview
Problem
3D stacked memory devices face challenges in fabricating and operating due to short circuit paths formed during plasma etching, where charges accumulate in conductive layers and diffuse into adjacent oxides, causing conductive paths and affecting select gate transistor control.
Innovation Solution
Incorporating a protective material with higher breakdown voltage than the oxide in the select gate layer to prevent short circuits, and using a bias voltage to detect and counteract any short circuits during operations, either by providing a discontinuous or continuous protective material such as a diode, capacitor, resistor, or varistor, or by determining an optimal bias voltage to prevent current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If plasma etching is used to form select gate lines, then memory device fabrication is enabled, but short circuit paths are formed due to charge accumulation and diffusion into adjacent oxides
Solution Approach 1:
A protective material layer is introduced as an intermediary between the select gate lines and the oxide layer. This protective material prevents charge carriers generated during plasma etching from diffusing into the oxide and forming short circuit paths, while still allowing the plasma etching process to proceed effectively.
Solution Approach 2:
The protective material is deposited beforehand on the oxide layer before plasma etching of the select gate lines. This pre-positioned protective layer cushions against the harmful effects of charge accumulation during etching, preventing short circuits before they can occur.
2Reliability
If protective material is added to prevent short circuits, then reliability is improved, but device complexity increases
Solution Approach 1:
The protective material's electrical parameters (high breakdown voltage, low conductivity) are specifically chosen to provide short circuit prevention. By adjusting the material's thickness and electrical properties, effective protection is achieved without excessively increasing structural complexity.
Solution Approach 2:
The select gate layer becomes a composite structure combining the oxide layer and the protective material layer. This composite structure provides both the original oxide functionality and the additional short circuit prevention capability of the protective material.
3Reliability
If bias voltage is applied to counteract short circuits, then proper transistor control is maintained, but energy consumption increases
Solution Approach 1:
Instead of applying continuous bias voltage, the patent applies bias voltage only partially - specifically during operations where short circuit risks are highest. This reduces energy consumption compared to continuous bias application while still maintaining proper transistor control when needed.
Solution Approach 2:
The protective material provides self-service by passively preventing charge diffusion without requiring active bias voltage application. The bias voltage is only used as a supplemental countermeasure when short circuits are detected, reducing overall energy consumption compared to continuous active prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents short circuits and ensures proper operation of select gate transistors, maintaining the integrity of memory cell programming, erasing, and reading processes by blocking current flow and maintaining selective control of select gate lines.
Implementation Method 1
a protective material having a higher breakdown voltage than the oxide in the select gate layer is provided to prevent short circuits
Implementation Method 2
using a bias voltage to detect and counteract any short circuits during operations, either by providing a discontinuous or continuous protective material such as a diode, capacitor, resistor, or varistor, or by determining an optimal bias voltage to prevent current leakage
Data Source
AI summary
In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit may occur when charges which are accumulated in select gate lines due to plasma etching, discharge through a remaining portion of the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates that the bias has exceed a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit.