Select Gate Spacer Structure for Split-Gate Flash Gap Fill
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Solution Overview
Problem
The integration of split gate flash memory cells with logic devices in integrated circuits faces challenges due to high aspect ratio gaps between memory cells, making dielectric fill operations difficult, and the need for spacer formation that maintains verticality without narrowing these gaps.
Innovation Solution
A method involving oxidation and atomic layer deposition (ALD) to form select gate sidewall spacers, where a portion of the select gate sidewall spacer is formed by oxidation, and another portion by ALD, ensuring uniform thickness and verticality without significantly narrowing the gaps, and allowing for a distinct composition of select gate spacers compared to logic gate spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional spacer formation methods are used to maintain verticality, then the gaps between memory cells are narrowed, but this makes dielectric fill operations difficult
Solution Approach 1:
The patent changes the formation method of the spacer from conventional deposition to oxidation, which fundamentally alters how the spacer material is deposited. This parameter change allows the spacer to form with vertical sidewalls while maintaining larger gap dimensions, resolving the contradiction between verticality and gap width
Solution Approach 2:
The patent replaces the mechanical deposition process with a chemical oxidation process. Instead of physically depositing spacer material that requires subsequent etching, the spacer is formed in-situ through oxidation of the select gate electrode, eliminating the need for complex spacer formation steps and allowing larger gaps to be maintained
2Ease of manufacture
If larger gaps between memory cells are implemented, then dielectric fill operations are improved, but the pitch increases
Solution Approach 1:
By changing the spacer formation mechanism from deposition to oxidation, the patent enables larger gap widths without proportionally increasing the overall pitch. The oxidation process creates spacers that are integrated with the select gate structure, allowing more efficient space utilization
3Device complexity
If select gate spacers have the same composition as logic gate spacers, then manufacturing is simplified, but select gate specific requirements cannot be met
Solution Approach 1:
The patent applies local quality by making the select gate spacer composition different from the logic gate spacer composition. The select gate spacer is formed through oxidation of the select gate electrode, giving it a distinct oxide composition that is tailored to the specific electrical and structural requirements of the select gate, while logic gate spacers can have different compositions optimized for their specific needs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates larger gaps between memory cells without increasing pitch, improving dielectric fill operations and maintaining verticality, thereby enhancing the manufacturing process efficiency and reliability of integrated circuits.
Implementation Method 1
oxidizing the select gates to form a first select gate spacer
Implementation Method 2
forming a second select gate spacer over the first select gate spacer with the second select gate spacer formed by atomic layer deposition
Data Source
AI summary
An integrated circuit device includes a semiconductor substrate having a memory area and a logic area. A memory cell in the memory area includes a select gate separated from a floating gate by a floating gate spacer. A select gate spacer is formed on a side of the select gate opposite the floating gate. The select gate spacer has a uniform thickness over most of the select gate. The first layer of the select gate spacer may be formed by oxidizing the select gate electrode. A second layer of the select gate spacer may be formed by atomic layer deposition. The memory area may be covered by a protective layer while spacers are formed adjacent logic gates in the logic region.