Select Gate Void Reduces Parasitic Coupling in Memory Stacks
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Solution Overview
Problem
Conventional NAND architectures face challenges in scaling to higher levels of integration due to difficulties in maintaining suitable electrical isolation between neighboring select gate configurations, leading to parasitic coupling and other problematic interactions as the spacing between select gates is reduced.
Innovation Solution
Incorporating a low-dielectric region, specifically a void with a low-k insulative composition, between neighboring select gate configurations to reduce parasitic capacitive coupling and improve electrical isolation, allowing for tighter packing of memory cells and increased integration levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If spacing between select gates is reduced to increase integration density, then memory cell packing density increases, but parasitic capacitive coupling between neighboring select gate configurations increases
Solution Approach 1:
A low-k dielectric material is introduced as an intermediary substance between neighboring select gate configurations. This intermediate layer acts as a mediator that reduces parasitic capacitive coupling while allowing the select gates to be positioned closer together, thereby enabling higher memory cell packing density without suffering from excessive parasitic effects.
Solution Approach 2:
The dielectric constant parameter of the material between select gates is changed from a conventional high-k material to a low-k dielectric material. This parameter change directly reduces the parasitic capacitive coupling between adjacent select gates, allowing for reduced spacing and increased integration density while maintaining electrical isolation.
2Productivity
If integration level is increased to improve productivity, then memory capacity increases, but electrical isolation between select gate configurations deteriorates
Solution Approach 1:
The low-k dielectric material serves as an intermediary that maintains electrical isolation between select gate configurations even at higher integration levels. By positioning this intermediary layer between adjacent select gates, the patent enables increased memory capacity while preserving the necessary electrical isolation through the low-parasitic coupling properties of the low-k material.
3Ease of manufacture
If select gate spacing is reduced to increase integration density, then manufacturing cost decreases, but process control difficulty increases
Solution Approach 1:
The low-k dielectric material is introduced as an intermediary layer that simplifies the manufacturing process by providing a built-in isolation mechanism. This intermediary layer allows for standard fabrication processes to be used even at reduced select gate spacings, thereby maintaining ease of manufacture while enabling higher integration density without compromising process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher levels of integration with improved electrical isolation and increased memory cell packing density, enhancing process margins and reducing undesired interactions between select gate configurations.
Implementation Method 1
Incorporating a low-dielectric region, specifically a void with a low-k insulative composition, between neighboring select gate configurations to reduce parasitic capacitive coupling and improve electrical isolation
Data Source
AI summary
Some embodiments include an assembly having a memory stack which includes dielectric levels and conductive levels. A select gate structure is over the memory stack. A trench extends through the select gate structure. The trench has a first side and an opposing second side, along a cross-section. The trench splits the select gate structure into a first select gate configuration and a second select gate configuration. A void is within the trench and is laterally between the first and second select gate configurations. Channel material pillars extend through the memory stack. Memory cells are along the channel material pillars.