Select Gate Line Voltage Control for Faster Memory Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high-speed read operations due to resistance imbalances between outer and inner select gate lines, leading to inefficiencies in voltage transitions during non-selected string discharge periods.
Innovation Solution
The implementation of a voltage generation circuit that independently controls voltages supplied to outer and inner select gate lines, adjusting resistance values within the driver circuit to ensure uniform voltage application and rapid transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single voltage control scheme is used for all select gate lines, then device complexity is reduced, but voltage transition speed and read operation performance deteriorate due to resistance imbalances
Solution Approach 1:
The select gate lines are segmented into outer select gate lines and inner select gate lines, with independent voltage control circuits for each segment. This segmentation allows differentiated voltage application strategies: higher voltages to outer lines for faster discharge, and controlled voltages to inner lines to prevent overshooting, thereby resolving the speed-complexity contradiction.
Solution Approach 2:
Different voltage control characteristics are applied to different spatial locations (outer vs. inner select gate lines). Outer lines receive aggressive voltage transitions for speed, while inner lines receive moderated voltage transitions for stability. This local quality differentiation optimizes overall read performance without uniformly increasing device complexity.
2Speed
If higher voltages are applied to accelerate voltage transitions, then read operation speed is improved, but voltage overshooting and disturbances increase
Solution Approach 1:
The patent applies different voltage control strategies to different spatial locations: outer select gate lines receive higher voltages for fast discharge, while inner select gate lines receive moderated voltages to prevent overshooting. This localized differentiation resolves the contradiction between speed and stability by optimizing voltage application for each region's specific electrical characteristics.
Solution Approach 2:
The voltage control circuit incorporates feedback mechanisms to monitor and adjust voltage application in real-time. When voltage transitions are detected, the control circuit modulates subsequent voltage pulses based on observed response, preventing overshooting while maintaining fast transition speeds. This feedback control ensures reliable operation during high-speed read operations.
3Manufacturing precision
If independent voltage control is implemented for outer and inner select gate lines, then voltage transition precision is improved, but device complexity increases
Solution Approach 1:
The voltage control system is segmented into dedicated control circuits for outer and inner select gate lines. Each segment handles specific voltage control tasks, simplifying the overall control logic while achieving precise voltage application. This segmentation approach balances precision requirements with circuit complexity by distributing control functions appropriately.
4Productivity
If voltage transitions are accelerated during non-selected string discharge, then read rate is improved, but disturbances to selected strings increase
Solution Approach 1:
The patent applies localized voltage control to different string groups during the discharge phase. Outer select gate lines (affecting non-selected strings) receive accelerated voltage transitions for high read rate, while inner select gate lines (affecting selected strings) receive moderated voltage transitions to minimize disturbances. This spatial differentiation resolves the contradiction between productivity and harmful effects.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.