3D NAND Select Gate Voltage Recalibration
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Solution Overview
Problem
The increasing density of memory cells in 3D NAND flash memory leads to reduced peripheral circuit area, limiting the drive capability of array voltage and resulting in longer program times due to slower voltage increases during programming.
Innovation Solution
A method for operating a memory that simultaneously erases and programs the select gate during the memory cell erase phase, recalibrating the threshold voltage of the select gate to prevent failure and ensure electrical separation, thereby improving reliability and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory density is increased by reducing peripheral circuit area, then the memory cell density is improved, but the drive capability of array voltage deteriorates resulting in longer program time
Solution Approach 1:
The patent applies preliminary action by performing an erase operation on the select gate before the program operation. This pre-erase step ensures the select gate starts from a known state (threshold voltage near 0V), which enables faster voltage rise during subsequent program operations. The erase phase includes applying high voltage to the select line while applying low voltage to the word line, preparing the select gate for optimal program performance.
Solution Approach 2:
The patent implements periodic action through the selective application of voltages in different phases. During the program phase, high voltage is periodically applied to the select line only during verify operations rather than continuously, allowing the select gate threshold voltage to be adjusted in steps. This periodic voltage application enables the threshold voltage to gradually approach the target value while maintaining reasonable program time.
2Device complexity
If the select gate threshold voltage is not recalibrated, then the circuit complexity is reduced, but the reliability deteriorates due to threshold voltage drift causing failure risk
Solution Approach 1:
The patent merges the erase operation of the select gate with the existing memory erase phase. By combining these operations, the select gate is erased simultaneously with the memory cells during the same time period, eliminating the need for a separate dedicated erase phase for the select gate. This merging approach maintains reliability through proper threshold voltage calibration while avoiding additional circuit complexity or extended operation time.
Solution Approach 2:
The select line serves multiple functions: it controls the select gate during read operations, performs erase operations on the select gate, and participates in program verify operations. This multi-functionality allows the same circuit infrastructure to be used for threshold voltage calibration without requiring additional dedicated circuits, thereby maintaining reliability while minimizing circuit complexity.
Data Source
AI summary
The present disclosure provides a method for operating a memory, a memory and a memory system, and relates to the technical field of semiconductor chip. The method includes: during the erase phase, applying an erase voltage to the word line, and applying an erase voltage to the select line coupled to a target select gate; during the program phase for select gate, applying a pass voltage to the word line, and applying a program voltage to the select line coupled to the target select gate.