Select Gate Transistor Voltage Waveform Control for 3D NAND Erase

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Solution Overview

Problem

In three-dimensional (3D) memory devices, there is a challenge in preventing inadvertent programming or erasing of select gate transistors and dummy memory cells during erase operations, particularly due to gate-induced drain leakage (GIDL) which can lead to improper voltage control and increased errors with accumulating program-erase cycles.

Innovation Solution

The solution involves a two-step voltage waveform approach for both erase and select gate voltages, where intermediate levels are set to allow channel charging without programming select gate transistors, and peak levels are incremented in each iteration to ensure complete erasure while maintaining a fixed difference to avoid select gate transistor erasure, with adjustments based on program-erase cycles or threshold voltage measurements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single-step high voltage waveform is applied to erase memory cells, then erase speed is improved, but select gate transistors are inadvertently programmed or erased due to GIDL

Engineering Contradiction:

Improveerase speedVSAvoidselect gate transistor threshold voltage control

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The erase operation is divided into multiple iterations with progressive voltage increments. Instead of applying a single high voltage step, the method segments the erase process into iterative steps where voltages are gradually increased until erase completion is detected, preventing GIDL-induced programming while maintaining efficient erase speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The method implements feedback by detecting whether the erase operation is complete and adjusting the voltage waveform accordingly. The controller monitors the erase status and modifies subsequent voltage applications to achieve complete erasure while preventing inadvertent programming of select gate transistors through controlled voltage sequencing.

Inventive Principle:

Principle #23Feedback

2Reliability

If intermediate voltage levels are used to prevent select gate programming, then select gate reliability is improved, but erase completeness may be compromised

Engineering Contradiction:

Improveselect gate transistor threshold voltage controlVSAvoiderase completeness

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The voltage waveform is made dynamic through iterative applications with progressive incrementing. The method starts with intermediate voltages to prevent GIDL programming, then increases voltages in subsequent iterations based on erase completion detection, ensuring both select gate protection and complete erasure are achieved.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The erase operation employs periodic voltage applications rather than a single continuous high voltage. Multiple periodic iterations allow the system to alternate between protective intermediate voltage phases and complete erasure phases, ensuring both select gate transistor integrity and thorough memory cell erasure.

Inventive Principle:

Principle #19Periodic action

3Productivity

If high drain-to-gate voltage is applied to charge the channel, then channel charging efficiency is improved, but select gate transistors are inadvertently programmed due to GIDL

Engineering Contradiction:

Improvechannel charging efficiencyVSAvoidGIDL-induced programming

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The method applies preliminary intermediate voltage levels before reaching the high voltages needed for efficient channel charging. By pre-charging the channel at lower voltages and then incrementally increasing voltage in iterative steps, the system achieves efficient channel charging while preventing GIDL-induced programming that would occur with immediate high voltage application.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively prevents inadvertent programming or erasure of select gate transistors, maintaining their threshold voltage within a specified range, thus ensuring accurate control and reliability of the memory device even after multiple cycles.

Implementation Method 1

there is a challenge in preventing inadvertent programming or erasing of select gate transistors and dummy memory cells during erase operations, particularly due to gate-induced drain leakage (GIDL)

Methodology Applied

Scientific EffectGate-induced drain leakage (GIDL):

Data Source

PatentUS9343159B2Avoiding unintentional program or erase of a select gate transistor

Publication Date: 2016.05.17 SANDISK TECHNOLOGIES LLC

AI summary

Techniques are provided for preventing inadvertent program or erase of select gate transistors and dummy memory cells during an erase operation involving data-storing memory cells in a three-dimensional memory device. The erase operation charges up a channel of a NAND string using gate-induced drain leakage from the select gate transistors. An erase voltage waveform and a select gate waveform are ramped up to intermediate levels which allow some charging of the channel to occur. The intermediate level of the select gate waveform is low enough to avoid inadvertent programming of the select gate transistors. Subsequently, the erase voltage waveform and the select gate waveform are ramped up to peak levels which allow additional charging of the channel to occur. The peak levels are set to avoid inadvertent erasing of the select gate transistors.