Adjusting Select Gate Transistor Threshold Voltage in 3D NAND Memory
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Solution Overview
Problem
The challenge in 3D stacked non-volatile memory devices is the variability of threshold voltage (Vth) for SGD transistors due to process variations and aging, which affects the conductivity and programming/erasing efficiency, making it difficult to maintain a narrow Vth distribution and optimize device performance.
Innovation Solution
A method for evaluating and adjusting the Vth of SGD transistors independently during die sort, involving reading at specific voltage levels to identify transistors below or above an acceptable range, and subsequently programming or erasing them to maintain the Vth within a specified window, allowing for periodic adjustments based on program-erase cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If process variations and aging are present in 3D stacked non-volatile memory devices, then manufacturing is simplified, but the threshold voltage distribution of SGD transistors becomes wide, affecting conductivity and programming/erasing efficiency
Solution Approach 1:
The patent applies preliminary action by performing threshold voltage evaluation and adjustment on SGD transistors during the die sort process, before the memory device is packaged and deployed. This advance adjustment narrows the Vth distribution caused by process variations and aging, ensuring optimal conductivity and programming/erasing efficiency from the outset, without requiring complex post-manufacturing interventions
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the threshold voltage of SGD transistors through controlled programming and erasing operations. By reading transistor characteristics at specific voltage levels and applying targeted programming/erasing pulses, the system modifies the Vth parameter to fall within an acceptable range, thereby narrowing the overall distribution and improving device performance
2Productivity
If threshold voltage of SGD transistors is not adjusted, then device operation is simpler, but programming and erasing efficiency deteriorates
Solution Approach 1:
The patent implements feedback by reading the threshold voltage of each SGD transistor at specific voltage levels (Vth_min and Vth_max) and using this information to determine whether programming, erasing, or no adjustment is needed. This feedback loop during die sort ensures that only transistors requiring adjustment are modified, optimizing programming and erasing efficiency while minimizing unnecessary operations
Solution Approach 2:
The patent applies preliminary action by performing threshold voltage adjustment during the die sort process, before the memory device enters production use. This advance adjustment ensures optimal programming and erasing efficiency from the start, eliminating the need for complex runtime adjustments or performance degradation over time
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.