3D Semiconductor Select Gate Work Function Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional microelectronic devices face challenges in increasing integration density and reducing write errors due to leakage current issues caused by differences in work functions between select and cell gate patterns during program operations.
Innovation Solution
The design incorporates a substrate with a vertical channel pattern, cell gate patterns, and a select gate pattern with a different work function, along with a charge storage pattern including a blocking and tunnel insulating layer, to suppress leakage current and enhance data storage reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If select gate pattern and cell gate pattern have the same work function, then manufacturing is simpler, but leakage current occurs during program operations
Solution Approach 1:
The patent applies local quality by assigning different work functions to different gate patterns based on their specific functional requirements. The select gate pattern has a first work function optimized for select transistor operation, while cell gate patterns have a second work function optimized for memory cell operation. This localized differentiation eliminates leakage current in select transistors during program operations while maintaining proper functionality across the device structure.
2Quantity of substance
If integration density is increased by vertical stacking, then more memory cells fit on substrate, but leakage current issues arise from work function differences
Solution Approach 1:
In the vertically stacked three-dimensional structure, each gate pattern is assigned a specific work function based on its location and function. Select gate patterns controlling select transistors have a first work function that prevents leakage, while cell gate patterns have a second work function for proper memory cell operation. This localized work function assignment throughout the vertical stack eliminates leakage current issues while maintaining high integration density.
3Reliability
If select gate pattern work function is increased to suppress leakage current, then program operation reliability improves, but device complexity increases
Solution Approach 1:
The patent implements parameter changes by modifying the work function parameter of gate patterns to different discrete values. Select gate patterns are assigned a first work function value optimized for preventing leakage current, while cell gate patterns are assigned a second work function value optimized for memory cell operation. This parameter differentiation provides a straightforward solution to the leakage problem without introducing structural complexity, as it only requires material composition or doping level adjustments during fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces write errors and boosts the cell string, improving the reliability and integration density of three-dimensional semiconductor devices.
Implementation Method 1
The select gate pattern has a different work function from at least one of the cell gate patterns... the work function of the select gate pattern may be greater than that of the cell gate pattern(s) when charges stored in the charge storage pattern during a program operation are electrons
Implementation Method 2
a charge storage pattern between the vertical channel pattern and the cell gate pattern
Implementation Method 3
the charge storage pattern may include a blocking insulating layer adjacent to the cell gate pattern, a tunnel insulating layer adjacent to the vertical channel pattern, and a charge storage layer between the blocking insulating layer and the tunnel insulating layer
Data Source
AI summary
A three-dimensional semiconductor device includes a vertical channel pattern on the substrate, a plurality of cell gate patterns and a select gate pattern stacked on the substrate along the sidewall of the vertical channel pattern, a charge storage pattern between the vertical channel pattern and the cell gate pattern and a select gate pattern between the vertical channel pattern and the select gate pattern. The select gate pattern has a different work function from the cell gate pattern.