Select-and-Insert Instructions for Faster 2D Array Addressing
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Solution Overview
Problem
Existing data processing systems face challenges in achieving high data throughput with low overhead, particularly in Viterbi decoding, due to the need for multiple instructions to access and manipulate two-dimensional arrays, leading to increased instruction cycles and energy consumption.
Innovation Solution
The introduction of an address calculation instruction that splits an input address value into two portions, adds a non-zero offset, and concatenates them to form an output address value, as well as a select-and-insert instruction for shifting and selecting bits, to reduce the number of instructions required for common processing tasks, enhancing efficiency and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two separate instructions are used to access two-dimensional array dimensions, then address manipulation flexibility is improved, but instruction cycle count and energy consumption increase
Solution Approach 1:
The patent combines multiple address manipulation operations into a single instruction. The address calculation unit performs splitting, offset addition, and concatenation operations within one instruction cycle, eliminating the need for multiple separate instructions to access two-dimensional array elements.
Solution Approach 2:
The patent segments the address value into multiple portions (first portion, second portion, third portion) that can be independently manipulated. This segmentation allows selective modification of specific address components while preserving others, enabling efficient two-dimensional array access patterns.
2Measurement precision
If multiple instructions are used for address calculations, then processing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple address calculation operations (splitting, offset addition, concatenation) into a single integrated instruction executed by the address calculation unit, reducing the number of instruction cycles while maintaining precise address manipulation capabilities.
Solution Approach 2:
The address calculation unit is designed as a universal component that can perform multiple operations (splitting at different positions, adding different offsets, concatenating portions) within a single instruction, eliminating the need for multiple specialized instructions.
3Productivity
If frequent address calculations are performed, then data access efficiency is improved, but energy consumption increases
Solution Approach 1:
The patent combines multiple address calculation operations into a single instruction cycle, reducing the number of execution cycles required for frequent data access operations and thereby lowering energy consumption while maintaining access efficiency.
Data Source
AI summary
A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon a size value into a first portion and second portion, adds a non-zero offset value to the first portion, sets the second portion to a value and then concatenates the result of the processing on the first portion and the second portion to form the output address value. Another type of instruction supported is a select-and-insert instruction. This instruction takes a first input value and shifts it by N bit positions to form a shifted value, selects N bits from within a second input value in dependence upon the first input value and then concatenates the shifted value with the N bits to form an output value. The address calculation instruction and the select-and-insert instruction described above are useful when manipulating two-dimensional data arrays, and particularly so when these are two-dimensional data arrays are formed of Viterbi trellis data through which traceback operations are to be performed.