Dynamic Select-Line Voltage During Memory Erase Suspend
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Solution Overview
Problem
Nonvolatile memory devices face challenges in suppressing changes in threshold voltages of select transistors during erase operations, particularly when suspend and resume commands are issued during the erase process, leading to inefficiencies and potential degradation.
Innovation Solution
The memory device incorporates a control logic system that manages the voltage differential between the erase voltage and select line voltage during rising and pulse application periods, adjusting the select line voltage to maintain a controlled voltage difference to minimize transistor threshold voltage changes and enhance erase operation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the erase voltage is applied at a high level during the pulse application period to ensure effective erasure, then the erasure effectiveness is improved, but the threshold voltage of select transistors decreases significantly due to gate-induced drain leakage
Solution Approach 1:
The patent applies dynamic voltage adjustment by changing the select line voltage based on the erase operation phase. During the rising period, a first voltage level is applied, and during the pulse application period, a second voltage level (different from the first) is applied. This dynamic adjustment optimizes both erasure effectiveness and threshold voltage stability at different stages of the erase operation.
Solution Approach 2:
The patent changes the voltage parameter of the select line during the erase operation. By adjusting the select line voltage to different levels during different periods (rising period vs. pulse application period), the patent controls the voltage differential to minimize threshold voltage degradation while maintaining effective erasure.
2Manufacturing precision
If the voltage differential between erase voltage and select line voltage is increased to suppress gate-induced drain leakage, then transistor threshold voltage stability is improved, but the erasure operation becomes less effective
Solution Approach 1:
The patent uses dynamic voltage adjustment where the select line voltage is set to different levels during different phases of the erase operation. During the rising period, one voltage level is used, and during the pulse application period, another voltage level is used, allowing optimization of both erasure effectiveness and threshold voltage stability at appropriate times.
Solution Approach 2:
The erase operation is divided into distinct periodic phases (rising period and pulse application period), with each phase having optimized voltage conditions. This periodic structure allows the system to alternate between conditions favoring erasure effectiveness and conditions favoring threshold voltage stability.
3Adaptability or versatility
If the erase operation is suspended and resumed multiple times during the pulse application period, then operational flexibility is improved, but the threshold voltage of select transistors degrades due to repeated voltage applications
Solution Approach 1:
The patent implements dynamic voltage control that adapts to suspend and resume operations. When the erase operation is resumed after suspension, the select line voltage is adjusted to an adjusted voltage level that accounts for previous voltage applications, thereby minimizing cumulative threshold voltage degradation while maintaining operational flexibility.
Solution Approach 2:
The system monitors the state of the erase operation and adjusts the select line voltage accordingly. Upon resumption, the voltage generating circuit applies an adjusted voltage level based on the operation history, creating a feedback mechanism that prevents excessive threshold voltage degradation from repeated suspend-resume cycles.
Data Source
AI summary
Provided is a memory device and a method of operating the same. The memory device includes a memory block including a plurality of memory cells, a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation, a page buffer group configured to apply the erase voltage to bit lines of the memory block during the erase operation, a voltage generating circuit configured to generate a select line voltage that is applied to a select line of the memory block during the erase operation, and control logic configured to control the source line driver, the page buffer group, and the voltage generating circuit to perform a suspend operation including suspending the erase operation in response to a suspend command.