Select RAM Mapping Logic for Error Data Crossbar Multiplexer Configuration

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Solution Overview

Problem

The complexity of configuring testers for multiple integrated circuits increases due to the traditional hardware-centric paradigm, which requires lengthy setup times and does not exploit similarities in device designs, especially when testing multiple identical devices.

Innovation Solution

A method and circuit that utilize a programmable Select RAM to selectively connect PE channels to error capture channels, allowing simultaneous configuration for multiple identical devices by associating DUT channels with PE channels and error data bit select configurations, reducing the need for explicit PE-channel-to-ECR-channel mapping for each device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional hardware-centric paradigm is used for configuring testers, then PE channels can be connected to ECR channels, but configuration time increases and throughput decreases

Engineering Contradiction:
Improvetester throughputVSAvoidconfiguration setup time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-configuring the Select RAM with PE channel to ECR channel mappings before actual testing begins. The Select RAM is loaded with configuration data that establishes the correct connections between PE channels and ECR channels in advance, eliminating the need for lengthy real-time configuration during test setup. This allows the tester to be quickly configured for multiple identical DUTs by simply loading pre-computed configuration data into the Select RAM.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If explicit PE-channel-to-ECR-channel mapping is performed for each device, then correct error data routing is achieved, but configuration complexity increases

Engineering Contradiction:
Improveerror data routing accuracyVSAvoidconfiguration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses copying by creating a reusable Select RAM structure that can be loaded with different PE channel to ECR channel mappings. Instead of manually configuring each connection for every device, the system copies the Select RAM configuration for multiple identical DUTs simultaneously. The Select RAM stores configuration data that can be rapidly loaded and reused, allowing the same hardware structure to serve multiple devices with different channel mappings without increasing operational complexity.

Inventive Principle:
Principle #26Copying

3Productivity

If multiple identical devices are tested simultaneously, then productivity improves, but configuration time remains lengthy due to hardware-centric paradigm

Engineering Contradiction:
Improvenumber of devices tested simultaneouslyVSAvoidtester configuration time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies universality by designing a single Select RAM structure that can serve multiple identical DUTs with different PE channel to ECR channel mappings. The Select RAM is a universal configuration storage that can be loaded with different mapping data for different devices, allowing the same hardware resource to support multiple device types without requiring separate configuration mechanisms for each device. This enables simultaneous testing of multiple identical devices by simply loading the appropriate configuration data into the Select RAM for each device.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7421632B2Mapping logic for controlling loading of the select ram of an error data crossbar multiplexer
Publication Date: 2008.09.02 ADVANTEST CORP
  • US7421632B2 patent drawing
  • US7421632B2 patent drawing
  • US7421632B2 patent drawing

AI summary

Methods and circuits for efficient configuration an error data crossover configuration circuit of an integrated circuit tester allows simultaneous DUT channel configuration for multiple identical DUTs for an error data control circuit.