3D Stacked Memory Select Transistor Boron Doping
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Solution Overview
Problem
In 3D stacked multilayer semiconductor memories, such as NAND and NOR flash memories, there is a challenge in performing doping in the channel region of select transistors to differentiate their doping concentration from memory transistors and establishing isolation between select and memory transistors, which affects reading latency and efficiency.
Innovation Solution
A lightly boron-doped layer is formed on top of a heavily boron-doped layer to create a select transistor channel, where the lightly doped P-type semiconductor layers function as channels and the heavily doped P-type semiconductor layers act as isolators, allowing for proper threshold voltage adjustment and isolation without deteriorating reading latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If electrical charge is injected to gate oxide of select transistor to change threshold voltage, then select transistor can be controlled, but reading latency deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the threshold voltage of select transistors through controlled boron doping during the fabrication process. The lightly boron-doped layer is formed in advance to establish the appropriate threshold voltage characteristics before the memory device begins operation. This eliminates the need for post-fabrication charge injection to gate oxide, thereby preventing reading latency deterioration while maintaining proper select transistor control.
2Reliability
If doping concentration of select transistor channel is differentiated from memory transistor channel, then select transistor performance is improved, but fabrication complexity increases
Solution Approach 1:
The patent applies local quality by creating a spatially differentiated doping structure where a lightly boron-doped layer is formed specifically in the select transistor channel region, while memory transistor channels maintain their original doping characteristics. This localized doping approach allows different doping concentrations in different functional regions (select transistor vs. memory transistor) without requiring completely separate fabrication processes for each transistor type, thus improving select transistor performance while limiting the increase in fabrication complexity.
Solution Approach 2:
The patent applies parameter changes by modifying the boron doping concentration parameter in the select transistor channel region. The lightly boron-doped layer introduces a specific doping concentration that differs from both the original select transistor channel and memory transistor channel doping levels. This parameter adjustment enables optimized select transistor performance through controlled threshold voltage modification without fundamentally changing the overall fabrication methodology.
3Reliability
If isolation structure is added between select transistor and memory transistor, then transistor isolation is achieved, but device structure becomes more complex
Solution Approach 1:
The patent applies universality by designing the lightly boron-doped layer to serve multiple functions simultaneously: it acts as the channel region for select transistors with appropriate threshold voltage characteristics, and it provides isolation between select transistors and memory transistors. This multi-functional structure eliminates the need for separate isolation structures, achieving transistor isolation while avoiding additional structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables suitable threshold voltage adjustment for select transistors without injecting electrical charges, improving reading speed and providing effective isolation between memory and select transistors, thus enhancing the performance of 3D stacked multilayer semiconductor memories.
Implementation Method 1
A boron-doped film is formed in a region of stacked layers where the select transistor channel is to be formed... wherein the heavily doped N-type semiconductor layers in the region are converted to lightly doped P-type semiconductor layers, and the lightly doped P-type (or undoped) semiconductor layers in the region are converted to heavily doped P-type semiconductor layers
Data Source
AI summary
In 3D stacked multilayer semiconductor memories including NAND and NOR flash memories, a lightly boron-doped layer is formed on top of a heavily boron-doped layer to form a select transistor, wherein the former serves as a channel of the select transistor and the latter serves as an isolation region which isolates the select transistor from a memory transistor.