3D Memory Select Transistor Charge Trapping Gate Dielectric
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming and operating select transistors with charge trapping gate dielectric layers, particularly in achieving reliable charge storage and control over threshold voltages in vertical NAND strings.
Innovation Solution
A three-dimensional memory device is designed with an alternating stack of insulating and electrically conductive layers, featuring a select gate electrode, memory stack structures with a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer, allowing for efficient charge trapping and control over threshold voltages through the use of silicon nitride and silicon oxide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge trapping gate dielectric layer is formed in the select transistor, then charge storage capability is improved, but device complexity increases
Solution Approach 1:
The gate dielectric layer is segmented into three distinct sub-layers: a tunneling gate dielectric layer (first sub-layer), a charge trapping gate dielectric layer (second sub-layer), and a cap gate dielectric layer (third sub-layer). This segmentation allows each layer to perform its specific function independently, improving charge storage capability while maintaining manageable device complexity through functional specialization.
Solution Approach 2:
The gate dielectric layer employs composite materials with different properties in each sub-layer. The tunneling layer uses materials suitable for charge injection, the charge trapping layer uses materials with high charge retention properties, and the cap layer uses materials for protection and field control. This composite structure optimizes charge storage while managing the complexity through material selection.
2Reliability
If the select transistor threshold voltage is reduced to minimize program disturb, then operational reliability is improved, but control over current flow becomes more challenging
Solution Approach 1:
The patent utilizes parameter changes in the gate dielectric layer properties to control the transistor threshold voltage. By adjusting the thickness, material composition, and charge trapping characteristics of the gate dielectric sub-layers, the threshold voltage is optimized to be sufficiently low to minimize program disturb while maintaining adequate control over current flow through the select transistor.
3Reliability
If a multi-layer gate dielectric structure is implemented, then charge trapping efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate dielectric layer is divided into three segmentable sub-layers that can be formed using sequential deposition processes. Each sub-layer can be independently controlled and optimized, allowing for manageable manufacturing precision requirements while achieving high charge trapping efficiency through the combined functionality of all layers.
Solution Approach 2:
Each sub-layer of the gate dielectric is designed with local quality optimized for its specific function. The tunneling layer has properties optimized for charge injection, the charge trapping layer has properties optimized for charge retention, and the cap layer has properties optimized for protection. This local optimization allows each layer to be manufactured with appropriate precision requirements rather than requiring uniform high precision throughout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the memory device's ability to store electrical charges and control current flow, improving isolation between word lines and minimizing program disturb due to low threshold voltage and short channel effects, thereby increasing operational reliability and efficiency.
Implementation Method 1
a tunneling gate dielectric layer, a charge trapping gate dielectric layer
Implementation Method 2
a charge trapping gate dielectric layer... allowing for efficient charge trapping
Data Source
AI summary
A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a horizontal semiconductor channel. An alternating stack of insulating layers and spacer material layers is formed over the gate dielectric layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conducive layers. Memory stack structures are formed through the alternating stack and the gate dielectric layer. Electrical charges can be injected into the charge trapping gate dielectric layer from the horizontal semiconductor channel to program the threshold voltage of a select field effect transistor employing a bottommost electrically conductive layer as a select gate electrode. The programmable threshold voltage can be advantageously employed to provide enhanced electrical isolation among word lines.