Selectable Clock Delay in Source Synchronous Interfaces
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Solution Overview
Problem
Current source synchronous type interfaces face challenges in configuring optimal delay settings for clock timing between transmitter and receiver devices, limiting flexibility and efficiency in data capture and transmission.
Innovation Solution
A source synchronous type interface system with a transmitter circuit and receiver circuit, utilizing a multiplexer and control circuit to selectively choose between a source clock and a ninety-degree phase-shifted clock for transmission, allowing for configurable delay settings at either the source or destination, enhancing configurability and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay on source (DoS) is used to generate the transmit clock by applying a ninety degree phase shift to the source clock, then the clock timing is optimized for data capture at the receiver, but the system loses flexibility in selecting different delay configurations
Solution Approach 1:
The patent implements a multiplexer that dynamically selects between different clock sources (phase-shifted source clock or destination clock) based on the desired delay configuration. This dynamic switching capability allows the system to adapt between DoS and DoD modes, resolving the contradiction by making the clock selection flexible rather than fixed to one configuration
2Ease of operation
If delay on destination (DoD) is used to generate the destination clock by applying a ninety degree phase shift to the transmit clock at the receiver, then the receiver can control clock timing, but the system lacks the ability to selectively choose between different delay locations
Solution Approach 1:
The patent creates a universal clock interface that can operate in multiple modes (DoS or DoD) through the multiplexer. The same hardware structure supports both delay-on-source and delay-on-destination configurations, allowing the receiver to control timing while maintaining the ability to select between different delay locations, thus achieving both ease of operation and adaptability
3Device complexity
If a fixed delay configuration is implemented in the source synchronous interface, then the circuit design is simplified, but the system cannot support various data transmission speeds and interface standards
Solution Approach 1:
The multiplexer acts as an intermediary component that enables flexible clock selection without significantly complicating the overall circuit design. By introducing this single selection mechanism, the system gains the ability to support various data transmission speeds and interface standards (such as Ethernet RGMII) while maintaining relatively simple circuit architecture
Data Source
AI summary
A transmitter circuit for use in a source synchronous type interface includes a flip-flop having a data input configured to receive serial data, a clock input configured to receive a source clock and a data output coupled to a data line. A first multiplexer has a first input configured to receive the source clock, a second input configured to receive a phase shifted clock (shifted by ninety degrees from the source clock), and a clock output coupled to a clock line. A control circuit operates to control selection by the first multiplexer of the source clock as a transmit clock sent over the clock line for a delay on clock at destination implementation. Alternatively, the control circuit causes selection by the first multiplexer of the phase shifted clock as the transmit clock sent over the clock line if the system is configured for a delay on clock at source implementation.