Selectable Clock Delay in Source Synchronous Transmitter Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing source synchronous type interface circuits lack configurability to effectively manage delay on source (DoS) and delay on destination (DoD) timing, which can lead to incorrect data capture and inefficient data transmission.
Innovation Solution
A transmitter circuit with a multiplexer and control circuit that selects between the source clock and a ninety-degree phase-shifted clock to configure the transmit clock for either delay on source or delay on destination configurations, allowing for enhanced timing flexibility and compatibility with various data transmission speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed delay configuration (either DoS or DoD) is used in source synchronous interface circuits, then the circuit structure is simple, but the interface lacks adaptability to different data transmission speeds and timing requirements
Solution Approach 1:
The patent implements a universal transmitter circuit that can operate in both DoS and DoD modes by incorporating a multiplexer that selects between different clock sources (phase-shifted clock for DoS, source clock for DoD). This allows a single circuit design to adapt to different timing configurations and data transmission requirements without requiring separate dedicated circuits for each mode.
Solution Approach 2:
The patent introduces dynamic configurability by allowing the delay configuration to be changed through control signals that switch between different clock paths. The multiplexer enables the circuit to dynamically select between the phase-shifted clock (providing DoS) and the source clock (providing DoD), making the timing behavior adaptable to different operating conditions and transmission speeds.
2Manufacturing precision
If delay on source (DoS) is implemented with a ninety-degree phase shift, then data capture timing is improved, but the circuit requires additional phase shifting components
Solution Approach 1:
The patent uses a multiplexer as an intermediary component that selects between different clock sources based on the desired operating mode. When DoS is required, the multiplexer selects the phase-shifted clock (which has been shifted by ninety degrees through a delay element) to clock the data output flip-flop, thereby achieving precise data capture timing without requiring complex phase shifting circuitry in all operating modes.
3Adaptability or versatility
If delay on destination (DoD) is implemented by phase shifting the received clock, then timing flexibility is improved, but the receiver circuit complexity increases
Solution Approach 1:
The patent designs the transmitter to provide both DoS and DoD capabilities through a single configurable circuit. By implementing the clock selection logic in the transmitter (using a multiplexer to choose between phase-shifted and source clocks), the receiver remains relatively simple while still achieving the desired timing flexibility. The transmitter's universal design eliminates the need for complex receiver-side phase shifting circuitry.
4Adaptability or versatility
If the interface supports multiple data transmission speeds, then versatility is improved, but the timing synchronization becomes more difficult to maintain
Solution Approach 1:
The patent implements dynamic clock selection that can adapt to different data transmission speeds. The multiplexer allows the circuit to switch between DoS and DoD modes depending on the operating conditions and speed requirements. This dynamic configurability maintains reliable timing synchronization across multiple data transmission speeds by selecting the appropriate clock path for each operating mode.
Data Source
Figure 1~2B
Figure 3~4
Figure 5
AI summary
A transmitter circuit (110) for use in a source synchronous type interface (116) includes a flip-flop (122) having a data input configured to receive serial data (Data), a clock input configured to receive a source clock (SRCCLK) and a data output (TXDATA) coupled to a data line (116d). A first multiplexer (104) has a first input configured to receive the source clock (SRCCLK), a second input configured to receive a phase shifted clock (PHSCLK - shifted by ninety degrees from the source clock), and a clock output (TXCLK) coupled to a clock line (116c). A control circuit (106) operates (dly_sel) to control selection by the first multiplexer (104) of the source clock (SRCCLK) as a transmit clock (TXCLK) sent over the clock line (106c) for a delay on clock at destination implementation. Alternatively, the control circuit (106) causes selection by the first multiplexer (104) of the phase shifted clock (PHSCLK) as the transmit clock (TXCLK) sent over the clock line (116c) if the system is configured for a delay on clock at source implementation.