Selectable Delay Buffers for Hold Timing in Ultra-Low-Voltage Circuits
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Solution Overview
Problem
Ultra low voltage circuits face challenges in maintaining optimal delay paths across varying voltage levels, leading to potential hold time violations and inefficient power performance, particularly in IoT and automotive applications.
Innovation Solution
The implementation of a selectable delay buffer with a combination of fixed and adjustable delay sections, utilizing PMOS and NMOS pass gates and multiplexers, allows for dynamic tuning of delay paths based on operating voltage levels, ensuring correct circuit operation and optimizing timing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed delay buffer is used in ultra low voltage circuits, then the circuit structure is simple, but the circuit cannot maintain optimal delay paths across varying voltage levels leading to hold time violations
Solution Approach 1:
The delay buffer is divided into multiple delay segments (first delay segment, second delay segment, third delay segment) with different delay characteristics. Each segment is optimized for specific voltage ranges, allowing the buffer to maintain optimal performance across varying voltage levels by selecting appropriate segments through control logic.
Solution Approach 2:
The delay buffer transitions from a fixed structure to a dynamic structure where delay segments can be selectively activated based on operating conditions. Control signals dynamically enable or disable specific delay segments according to voltage level and clock frequency, ensuring optimal delay path selection without manual reconfiguration.
2Productivity
If delay segments are selectively activated based on voltage levels, then timing characteristics are optimized, but control circuit complexity increases
Solution Approach 1:
The control logic monitors operating parameters (voltage level and clock frequency) and dynamically adjusts the activation state of delay segments based on these parameters. When voltage increases or frequency decreases, the control logic enables additional delay segments to maintain optimal timing characteristics, automatically adapting to parameter changes without external intervention.
Solution Approach 2:
The control circuit receives feedback about the operating conditions (voltage and frequency) and uses this information to determine which delay segments should be active. This feedback mechanism ensures that the delay buffer automatically compensates for voltage-frequency variations, maintaining timing closure across different operating points.
3Reliability
If delay segments are selectively activated based on frequency, then timing characteristics are optimized, but control circuit complexity increases
Solution Approach 1:
The control logic responds to frequency parameter changes by adjusting delay segment activation. At lower clock frequencies, additional delay segments are enabled to maintain minimum delay requirements and prevent hold time violations. At higher frequencies, fewer segments are active to reduce unnecessary delay and power consumption.
Data Source
AI summary
Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.