Selectable Delay Line Using Weighted Tap Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electronic circuits for delaying clock signals consume power, introduce noise, and are affected by process, voltage, and temperature (PVT) variations, making them inefficient and unreliable.
Innovation Solution
An electronic circuit with a delay line and multiple tap locations, coupled with switches that induce a delay independent of PVT variations by using physical propagation down a metal line, allowing for fine control over delay without power consumption or noise addition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffers are used to delay clock signals, then delay functionality is achieved, but power consumption increases and noise is introduced
Solution Approach 1:
The patent replaces active electronic buffers with a passive delay line implemented as a metal interconnect structure. This mechanical/physical substitution eliminates the need for powered active components, achieving delay functionality without power consumption or noise generation. The delay is achieved through the physical propagation time of signals through the metal line structure.
Solution Approach 2:
The patent extracts the delay functionality from active buffer components and implements it through passive metal interconnect structures. By separating the delay function from powered components, the design eliminates power consumption and noise while maintaining the essential delay capability needed for clock signal timing.
2Loss of time
If more buffers are used to increase delay, then delay amount increases, but power consumption and noise increase proportionally
Solution Approach 1:
The patent replaces the sequential buffering approach with a parallel metal interconnect delay line. Instead of cascading multiple powered buffers to achieve longer delays, the design uses the physical length and propagation characteristics of metal lines to provide the required delay without additional power consumption.
Solution Approach 2:
The patent segments the delay line into multiple tapped sections along the metal interconnect. This allows selective access to different delay points without requiring additional active components, enabling flexible delay adjustment while maintaining low power consumption throughout the structure.
3Reliability
If buffers are used for delay, then delay is achieved, but the delay varies with PVT (process, voltage, temperature) variations
Solution Approach 1:
The patent replaces voltage-dependent buffer-based delay with physics-based metal interconnect delay. The propagation delay through metal lines is determined by physical dimensions and material properties rather than voltage levels, making it inherently more stable against PVT variations and improving delay reliability.
4Reliability
If active delay elements are used, then delay functionality is achieved, but device noise is added to the signal
Solution Approach 1:
The patent extracts the delay function from active noisy components and implements it through passive metal interconnects. This separation removes the noise-generating elements while preserving the timing functionality, resulting in cleaner clock signals suitable for high-precision applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a PVT-invariant signal delay with low power and noise, enabling precise control over clock signals, which is essential for high-speed analog-to-digital converters and other applications.
Implementation Method 1
Delay is induced using physical propagation of the signal down a metal line (delay line)
Data Source
AI summary
In described examples, an electronic circuit for delaying a signal (received at an input node) includes a delay line with multiple tap locations, a tap line proximate to the delay line and coupled to an output node, and multiple groups of switches. Switches in the groups of switches are severally coupled between tap locations corresponding to the respective group of switches, and the tap line. When the signal is propagated through the delay line, a first number of the switches corresponding to a selected tap location are closed, a second number of the switches corresponding to an adjacent tap location are closed, and the signal is transmitted with a delay through the closed switches, to the tap line, to the output node. The delay includes an average, weighted using the first and second numbers, of delays corresponding to the selected and adjacent tap locations.