Selectable-Rate CDR Circuit With Dual-Loop Jitter and Power Control
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Solution Overview
Problem
High-performance clock and data recovery (CDR) circuits consume substantial power, especially at low supply voltages, and suffer from increased jitter due to reduced tuning range, which limits their ability to handle noise and maintain stable clock recovery in high-speed data transmission systems.
Innovation Solution
The CDR circuit employs an active differential capacitor bank to extend the tuning range of the voltage-controlled oscillator (VCO) and incorporates a dual-loop power control method to reduce power consumption, along with selectable rate and phase output capabilities through a combination of fixed-rate and variable-rate down-sampling, using a line rate CDR circuit, a fixed-rate down-sampler, and a variable-rate down-sampler.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a conventional CDR circuit operates at low supply voltages to reduce power consumption, then power consumption is reduced, but jitter increases due to reduced tuning range
Solution Approach 1:
The CDR circuit is divided into two independent loops: a coarse frequency acquisition loop and a fine phase tracking loop. This segmentation allows each loop to be optimized independently - the coarse loop provides wide tuning range for frequency acquisition while the fine loop provides high precision for phase tracking, resolving the contradiction between power consumption and jitter performance
Solution Approach 2:
The circuit dynamically switches between coarse frequency acquisition mode and fine phase tracking mode based on lock status. During acquisition, the coarse loop is active with wide tuning range; after lock is achieved, the fine loop takes over with high precision. This dynamic operation maintains low power consumption while ensuring low jitter during normal operation
2Reliability
If a line rate CDR circuit is used to maintain high precision clock recovery, then jitter performance is improved, but power consumption increases substantially
Solution Approach 1:
The invention extracts only the essential timing information from the high-speed data stream using a simplified recovery circuit, rather than processing the entire high-speed signal through a full line-rate CDR. This extraction approach maintains adequate jitter performance for the application while dramatically reducing power consumption by avoiding the need for high-speed sampling and processing
3Use of energy by stationary object
If a fixed-rate down-sampler is used to reduce data rate, then power consumption is reduced, but flexibility in selecting output phase and rate is lost
Solution Approach 1:
The fine phase tracking loop is designed to provide both frequency division and phase selection capabilities in a single circuit block. By using a programmable divider and phase selector controlled by the state machine, the circuit can output multiple different rates and phases from the same hardware, maintaining flexibility while keeping power consumption low compared to multiple dedicated down-samplers
4Adaptability or versatility
If a variable-rate down-sampler is added to provide flexible output rates, then adaptability is improved, but device complexity increases
Solution Approach 1:
The variable-rate down-sampling functionality is merged with the fine phase tracking loop rather than being implemented as a separate circuit block. The phase detector, voltage-controlled delay element, and programmable divider are integrated into a single unified structure that performs both phase tracking and flexible rate conversion, reducing overall device complexity while maintaining full adaptability
Data Source
AI summary
A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.