Selectable Timer Unit Circuit for Multi-Mode PWM Output

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Solution Overview

Problem

The development of microcontrollers with timer unit circuits for motor control is hindered by high costs due to the need for dedicated designs, limiting versatility and flexibility in control operations.

Innovation Solution

A timer unit circuit with a selection mechanism that allows for multiple counter circuits and output modes, enabling synchronization with various clock signals and trigger signals, and the ability to switch between different output modes for PWM waveform generation, thereby enhancing versatility and flexibility in control operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dedicated timer unit circuit is designed for specific motor control applications, then control performance is improved, but development costs increase

Engineering Contradiction:

Improvecontrol performanceVSAvoiddevelopment costs

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The timer unit circuit is designed with multiple output circuits (first output circuit and second output circuit) that can be selectively activated based on operation mode. The circuit can function as a dedicated motor control timer when needed, or as a general-purpose timer, allowing one hardware design to serve multiple application needs and reduce development costs for different motor control configurations

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple separate timer circuits are provided for different control modes, then control versatility is improved, but device complexity increases

Engineering Contradiction:

Improvecontrol versatilityVSAvoidcircuit complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Multiple output circuits are merged into a single timer unit circuit with shared counter circuits. The first output circuit generates PWM waveforms for normal operation, while the second output circuit handles reversed-phase PWM waveforms for braking operations. This consolidation allows different control modes to be achieved within one integrated circuit rather than requiring separate timer units, thereby reducing overall device complexity

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The output circuits are designed to dynamically switch between different output modes based on operation requirements. The circuit can transition between generating normal-phase PWM waveforms, reversed-phase PWM waveforms, or stopping output entirely, allowing the same hardware to adapt to varying control needs without requiring physical reconfiguration or additional dedicated circuits for each mode

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8117482B2Timer unit circuit having plurality of output modes and method of using the same

Publication Date: 2012.02.14 RENESAS ELECTRONICS CORP

AI summary

First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock signal, the trigger signal and the clock signal. In a first output mode, an output circuit outputs signals exhibiting normal-phase and reversed-phase PWM waveforms based on both of the signals of the first and second counter circuits. In a second output mode, the output circuit outputs signals that are each based only on either of the signals of the first and second counter circuits.