Selectable Vias for BEOL Interconnect RC Delay
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Solution Overview
Problem
The continued downscaling of integrated circuits leads to increased resistance-capacitance (RC) delay due to the shrinking dimensions of interconnects, resulting in performance degradation and the need for larger numbers of interconnects, which are difficult to manage effectively.
Innovation Solution
The implementation of selectable vias with a thin film transistor structure that can be ad hoc selected or deselected, allowing signals to pass through or be blocked, enabling multiple vias to share a global interconnect, thereby reducing the number of interconnects and improving RC performance by increasing interconnect size and spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interconnect dimensions are downscaled to increase the number of interconnects, then the quantity of interconnects is improved, but resistance-capacitance delay increases and performance degrades
Solution Approach 1:
Multiple local interconnects are merged into a single shared global interconnect through the use of selectable vias. Instead of providing separate global interconnects for each local interconnect, the patent combines multiple local interconnects (first, second, third local interconnects) to share a common global interconnect, thereby reducing the total number of global interconnects while maintaining connectivity options.
Solution Approach 2:
The selectable via structure introduces dynamic routing capability where the connection between local and global interconnects can be changed ad hoc. The via can be selectively activated or deactivated to connect different local interconnects to the global interconnect, allowing the interconnect topology to be reconfigured based on performance requirements.
2Adaptability or versatility
If the number of interconnects is increased to compensate for downscaling effects, then connectivity is improved, but device complexity and difficulty of management increase
Solution Approach 1:
The global interconnect is designed to serve multiple local interconnects simultaneously. A single global interconnect can be dynamically connected to different local interconnects based on routing needs, making the global interconnect universal in its functionality rather than dedicated to a single local interconnect.
Solution Approach 2:
The interconnect system is segmented into local interconnects and a global interconnect with selectable vias providing the interface. This segmentation allows independent optimization of local and global routing while reducing the overall complexity by separating concerns between local connectivity and global routing.
Data Source
AI summary
Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.