Selected Gate Driver Circuit for High-Speed NVRAM Read Accuracy
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Solution Overview
Problem
Existing selected gate (SG) driver circuits in non-volatile memory (NVRAM) devices face challenges in accurately executing read operations at high speeds due to competition between MOS transistors during the short word line preparation phase, leading to inaccurate read operations.
Innovation Solution
The proposed SG driver circuit incorporates a specific configuration of NMOS and PMOS transistors, along with a control method that applies logic high and low voltage levels to the transistors at different phases of the read operation, ensuring accurate execution by avoiding competition between the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the NVRAM is operated in high speed, then the productivity is improved, but the word line preparation phase becomes too short causing competition between MOS transistors and inaccurate read operations
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a specific voltage level before the read operation begins. The bit line is charged to a first voltage level during the idle phase, and this pre-charged state is maintained through the word line preparation phase. This preliminary charging ensures that when the read operation executes quickly at high speed, the bit line is already in the correct initial state, eliminating the need for a longer preparation phase and preventing transistor competition while maintaining read accuracy.
2Reliability
If the word line preparation phase is extended to avoid transistor competition, then the read operation accuracy is improved, but the operating speed of the NVRAM decreases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage levels applied to different transistors based on the operational phase. During the word line preparation phase, specific voltage levels are applied to control the switching behavior of MOS transistors, ensuring they remain in a non-competitive state. During the execution phase, voltage parameters are changed to enable proper read operation. This dynamic parameter adjustment allows accurate read operations without requiring an extended preparation phase, maintaining high operating speed.
Data Source
AI summary
A selected gate (SG) driver circuit, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor. A source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor.