Selection Structure Layout for Dense Semiconductor Signal Routing
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Solution Overview
Problem
Challenges arise during the scaling-down process of semiconductor devices, affecting quality, yield, performance, and reliability, and there is a need to optimize semiconductor real estate for increased functionality.
Innovation Solution
A semiconductor device design featuring selection structures and vias that allow for multiple signal paths to be formed based on user programming, utilizing a first and second top selection structure, a first and second ground layer, and a first and second bottom selection structure, with overlapping and via configurations to optimize semiconductor real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the dimensions of semiconductor devices are scaled down to meet increasing computing demand, then computing ability is improved, but quality, yield, performance, and reliability deteriorate
Solution Approach 1:
The selection structure is divided into multiple separate components including a first selection structure, a second selection structure, a third selection structure, and a fourth selection structure. Each selection structure is further segmented into top and bottom portions with intervening spaces, allowing independent optimization and reduced相互 interference, thereby maintaining reliability while enabling scaling
Solution Approach 2:
The patent introduces vertical layering with selection structures positioned at different vertical levels (first vertical level for top structures, second vertical level for bottom structures). This three-dimensional arrangement increases functional density without compromising planar scaling, enabling improved computing ability while maintaining device reliability through spatial separation
2Speed
If the dimensions of semiconductor devices are scaled down, then computing ability is improved, but manufacturing complexity increases
Solution Approach 1:
Multiple selection structures (first, second, third, and fourth) share common architectural features including top and bottom portions with intervening spaces, standardized via connections, and uniform insulating layer configurations. This modular universal design reduces manufacturing complexity by enabling repeated use of the same fabrication processes across different selection structures
Solution Approach 2:
The selection structures are arranged with nested spatial relationships where top portions extend in first and second directions, bottom portions extend in corresponding directions, and ground layers are positioned between them. This nested configuration allows multiple functional elements to be integrated within a compact footprint, improving computing density while managing manufacturing complexity
3Area of stationary object
If selection structures are positioned close to the main signal pad to save space, then semiconductor real estate is optimized, but signal interference and reliability issues increase
Solution Approach 1:
Ground layers are positioned between the selection structures and the main signal pad, serving as intermediary elements that provide electrical isolation and signal shielding. This intermediary configuration allows selection structures to be positioned close to the main signal pad for space optimization while maintaining signal integrity through the protective ground layer barrier
Solution Approach 2:
Selection structures are arranged in three-dimensional space with top portions at a first vertical level and bottom portions at a second vertical level, creating vertical separation from the main signal pad. This vertical dimensionality allows horizontal proximity for space efficiency while maintaining electrical isolation through the vertical spacing and ground layer positioning
Data Source
AI summary
A semiconductor device includes a first top selection structure and a second top selection structure at a same vertical level as and separated from a main signal pad, and respectively extending along different directions; a first ground layer at the same vertical level as and separated from the main signal pad and the top selection structures; a first bottom selection structure at a vertical level lower than the main signal pad and partially overlapped with the top selection structures and the first ground layer in a top-view perspective; a first top via between the first ground layer and the first bottom selection structure; second top vias between the top selection structures and the first bottom selection structure; first insulating layers between the second top vias and the first bottom selection structure; and a wiring pad on the main signal pad and the top selection structures.