Selection Transistor Capacitive Boosting for Low Power Memory
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Solution Overview
Problem
Nonvolatile semiconductor memory devices face challenges in reducing power consumption and chip area while achieving high-speed data reading, due to issues like over-erasure and the complexity of threshold voltage control, which leads to increased costs and power consumption.
Innovation Solution
A nonvolatile semiconductor memory device with a series body of stacked gate transistors and selection transistors, where the voltage levels of the selection transistors are set individually using separate voltage setting circuits, allowing for capacitive boosting and reducing the need for a charge pump circuit, thereby minimizing current consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a charge pump circuit is used to boost gate voltage for reading data, then high-speed data reading is achieved, but current consumption and chip area increase
Solution Approach 1:
The patent extracts and eliminates the charge pump circuit from the memory device architecture. By using a selection transistor with individually controllable gate electrodes, the device achieves high-speed reading without requiring the charge pump circuit that normally provides voltage boosting, thereby removing the source of high current consumption and large chip area.
Solution Approach 2:
The selection transistor is designed with multiple gate electrodes that can be independently controlled to perform multiple functions: selecting memory cells, boosting gate voltage through capacitive coupling, and enabling high-speed reading operations. This multi-functional design replaces the need for separate charge pump circuitry.
2Speed
If a charge pump circuit is used to boost gate voltage, then high-speed data reading is achieved, but chip area increases
Solution Approach 1:
The patent removes the charge pump circuit from the device architecture entirely. The selection transistor's gate electrodes provide voltage boosting through capacitive coupling, eliminating the need for dedicated charge pump circuitry and its associated large chip area.
Solution Approach 2:
The voltage boosting function is nested within the selection transistor structure itself. The stacked gate electrodes of the selection transistor are positioned such that they can capacitively couple to provide voltage boosting, integrating the boosting function into the existing transistor geometry without requiring additional external circuits.
3Reliability
If threshold voltage is set low to prevent over-erasure, then data reading reliability improves, but data cannot be read under low power supply voltage
Solution Approach 1:
The patent applies preliminary voltage boosting to the selection transistor gate electrodes before data reading operations. By capacitively coupling voltage from the stacked gate electrodes, the selection transistor achieves high conductivity state that enables reliable data reading even when the memory cell transistor has low threshold voltage, thus supporting low power supply voltage operation.
Solution Approach 2:
The patent changes the voltage parameters of the selection transistor gate electrodes dynamically. By individually controlling the voltage levels of the first and second gate electrodes, the selection transistor's conductivity can be optimized for different operating conditions, enabling reliable reading at low power supply voltages while maintaining the ability to operate at higher voltages when needed.
4Use of energy by moving object
If separate voltage setting circuits are used for each gate electrode of selection transistor, then capacitive boosting is enabled and charge pump circuit is reduced, but device complexity increases
Solution Approach 1:
The patent segments the voltage control into separate circuits for each gate electrode of the selection transistor. The first voltage setting circuit controls the first gate electrode and the second voltage setting circuit controls the second gate electrode independently. This segmentation enables precise capacitive coupling control while distributing the complexity across multiple simple, independent circuits rather than one complex charge pump circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed and stable data reading with low current consumption, simplifies the erasure sequence, and reduces the chip area by eliminating or minimizing the charge pump circuit, addressing the challenges of over-erasure and power consumption.
Implementation Method 1
the voltage levels of the selection transistors are set individually using separate voltage setting circuits, allowing for capacitive boosting
Data Source
AI summary
In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.