Selective Aluminum Oxide Etch for Fin-etched Substrates
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Solution Overview
Problem
Current photolithographic techniques face limitations in reducing feature size of integrated circuits due to minimum pitch restrictions, leading to increased defects and low production yields from pattern misalignment and tight geometric requirements.
Innovation Solution
The method involves forming a spin-on-carbon layer, hardmask, and photoresist on a film with alternating columns of spacer mandrels and gapfill materials, followed by selective etching to expose and remove layers, ultimately achieving precise patterning and alignment through a two-color hardmask scheme and spacer-on-spacer AB mask process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography techniques are used to pattern ICs, then manufacturing capability is improved, but minimum pitch restrictions limit further feature size reduction
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple discrete steps (SADP, SAQP, LELE) that build upon each other. Each step creates additional patterns from previous structures, effectively segmenting the overall fabrication sequence to achieve sub-lithographic pitch features through cumulative pattern formation rather than attempting to create all features in a single photolithography step.
Solution Approach 2:
The patent utilizes another dimension by transitioning from planar 2D patterning to 3D vertical structures through self-aligned double patterning and quad patterning. The process creates multi-layered mask stacks and vertically stacked patterns, adding a vertical dimension to the patterning approach that enables achieving pitch resolutions below the lateral diffraction limits of conventional photolithography.
2Manufacturing precision
If multi-cut or block masks are placed over lines and spaces generated by SADP, SAQP, or LELE processes, then device patterning is achieved, but precision of mask edge placement control must be extremely high
Solution Approach 1:
The patent applies self-service through self-aligned patterning processes where previously formed structures automatically serve as alignment references for subsequent patterning steps. The spacer mandrels and gapfill materials created in earlier SADP/SAQP/LELE steps automatically define the positions of next-generation features, eliminating the need for external alignment operations and reducing mask edge placement errors without requiring additional alignment equipment or complex procedures.
Solution Approach 2:
The patent implements preliminary action by pre-forming spacer mandrels and gapfill materials in advance before the final device patterning step. These preliminary structures are created with high precision through self-aligned processes, and they subsequently serve as templates that guide the placement of final device features. This preliminary structuring establishes a high-precision reference framework that simplifies subsequent patterning operations and reduces cumulative alignment errors.
3Manufacturing precision
If tight geometric requirements are imposed on masks, then device patterning precision is improved, but production yields decrease
Solution Approach 1:
The patent applies self-service by using previously formed spacer mandrels and gapfill structures as self-aligning references for subsequent patterning steps. This self-alignment mechanism automatically compensates for minor variations in feature dimensions and positions, reducing the stringency of geometric requirements on masks while maintaining high patterning precision. The self-referential nature of the process reduces sensitivity to geometric tolerances, thereby improving production yields without sacrificing edge placement accuracy.
Solution Approach 2:
The patent implements parameter changes by transitioning from single-step direct patterning to multi-step self-aligned patterning sequences. This changes the critical parameters from direct mask-to-feature alignment accuracy to relative spacing consistency between self-aligned structures. The process parameters shift from requiring extreme absolute geometric precision to requiring consistent relative positioning, which is more easily controlled and less sensitive to variations, thereby improving both precision and yield simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes pattern misalignment and increases production yields by allowing for more precise control over edge placement errors, enabling the formation of smaller feature sizes and reducing defects in integrated circuit patterning.
Implementation Method 1
The spin-on-carbon layer, hardmask and gapfill material are removed to leave a gap in the film
Implementation Method 2
The oxide films are removed to leave spacer mandrels and gapfill materials on an etch stop layer on an oxide layer on a substrate
Implementation Method 3
The etch stop layer and the oxide layer not covered by the spacer mandrels or gapfill materials are removed
Implementation Method 4
The expose portions of the substrate are fin etched
Data Source
AI summary
Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide and/or silicon nitride are described. Certain embodiments relate to the formation of fin-etched substrates. Other embodiments relate to the removal of source drain caps from substrates. Further embodiments relate to the processing of substrates comprising vias and/or metal contacts with bottom etch stop layers and/or liner layers.