Selective Amorphization for Signal Isolation in Semiconductor Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Silicon on Insulator (SOI) applications face challenges in achieving high noise isolation and low signal loss due to the combination of a low resistivity top semiconductor layer and an inversion layer at the base oxide-handle wafer interface, which results in a lossy, non-linear network, especially at high frequencies and power levels, and the effectiveness of isolation trenches decreases as the available area diminishes.
Innovation Solution
The method involves selective amorphization of the handle wafer surface through high energy inert implants, such as Xenon or Argon, to create amorphized regions that increase impedance and path length for electrical signals, allowing for improved isolation and linearity beyond the limitations of conventional trench-based approaches by spanning the entire dimension of the handle wafer surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation trenches are used to provide noise isolation and low signal loss, then electrical signal isolation is improved, but the effectiveness decreases as the available area for trenches diminishes
Solution Approach 1:
The patent changes the physical state of the handle wafer material from crystalline to amorphous through ion implantation. This parameter change creates high resistance regions that provide electrical signal isolation without requiring trench structures, thereby resolving the contradiction between achieving isolation and maintaining available area.
Solution Approach 2:
The patent replaces the mechanical trench-based isolation system with a field-based approach using amorphized regions. Instead of physically removing material to create trenches, the invention uses ion implantation to alter the electrical properties of the handle wafer, substituting a mechanical structure with a material property modification.
2Reliability
If a low resistivity top semiconductor layer is used for active devices, then device performance is improved, but signal loss increases due to the inversion layer at the base oxide-handle wafer interface
Solution Approach 1:
The patent applies local quality by creating amorphized regions with high resistance at specific locations in the handle wafer beneath active devices. This localized modification allows the top semiconductor layer to maintain low resistivity for device performance while the underlying amorphized regions provide signal isolation, preventing energy loss through the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical signal isolation and linearity by increasing impedance between adjacent devices and reducing substrate-related losses, providing superior isolation and linearity across the entire active device substrate rather than just the trench periphery, thus overcoming the limitations of conventional SOI structures.
Implementation Method 1
The method involves selective amorphization of the handle wafer surface through high energy inert implants, such as Xenon or Argon
Implementation Method 2
create amorphized regions that increase impedance and path length for electrical signals
Data Source
AI summary
Provided is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and a method for the structure's fabrication. The structure comprises a gate situated on the top semiconductor layer, the top semiconductor layer situated over a base oxide layer, and the base oxide layer situated over a handle wafer. The top surface of the handle wafer is amorphized by an inert implant of Xenon or Argon to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.