Selective Area Regrown III-Nitride HEMT
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Solution Overview
Problem
High-power fluorine etching in the manufacturing of AlInN--GaN high-electron-mobility transistors (HEMTs) causes material damage, increases leakage currents, and leads to premature breakdown, necessitating the development of methods that avoid such high-power etching.
Innovation Solution
A method for forming HEMT devices on thin film layers that includes forming an ultra-thin barrier layer, depositing a dielectric thin film layer, and selectively growing a source-drain layer while exposing the barrier layer to fluorine treatment without the need for high-power etching, followed by the deposition of a dielectric coating and gate electrode, thereby avoiding recess etching steps and utilizing pulsed deposition techniques for high-quality silicon dioxide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-power fluorine etching is used in the manufacturing of AlInN-GaN HEMTs, then material removal and recess formation are achieved, but material damage occurs, leakage currents increase, and premature breakdown results
Solution Approach 1:
The patent converts the harmful high-power fluorine etching process into a beneficial low-power process by using a multi-layer structure (ultra-thin barrier layer, dielectric layer, SAG S-D layer) that enables recess formation without high-power etching. The dielectric layer acts as a protective mask that allows precise recess formation through selective area re-growth while preventing the material damage and leakage current issues caused by high-power fluorine etching.
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between the ultra-thin barrier layer and the SAG S-D layer. This dielectric layer serves as a protective mask during the selective area re-growth process, enabling precise control of the recess formation without requiring high-power fluorine etching. The intermediary layer prevents direct exposure to harsh etching conditions while still allowing the desired structural modifications.
2Ease of manufacture
If conventional fluorine based gate recessing process is used, then HFET fabrication is achieved, but leakage currents increase and breakdown occurs prematurely
Solution Approach 1:
The patent converts the harmful conventional fluorine based gate recessing process into a beneficial alternative by using selective area re-growth with a dielectric mask. This approach maintains the ease of fabrication through standard semiconductor processing techniques while eliminating the leakage current and premature breakdown issues associated with high-power fluorine etching.
Solution Approach 2:
The patent changes the key parameter of the etching process from high-power to low-power fluorine treatment. By using low-power fluorine in conjunction with the dielectric mask and selective area re-growth technique, the process achieves the same structural modification (gate recess formation) without the harmful effects of high-power etching, thus improving device reliability while maintaining manufacturability.
3Reliability
If ultra-thin barrier layer with thickness of 0.2 nm to 20 nm is formed, then carrier confinement is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The dielectric layer serves as an intermediary that protects the ultra-thin barrier layer during subsequent processing steps. This protective mask allows the ultra-thin barrier layer to be formed with precise thickness control (0.2 nm to 20 nm) without exposing it to the harsh conditions of high-power etching, thereby maintaining both the carrier confinement benefits and the manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces channel thickness, increases the gate width to channel thickness ratio, enhances carrier confinement, and results in higher output current and power at higher frequencies, while minimizing trap and defect densities and avoiding side-wall leakage, leading to improved performance and reliability of HEMT devices.
Implementation Method 1
enhances carrier confinement
Implementation Method 2
The underlying ultra-thin barrier layer exposed by removal of the dielectric thin film layer can then be treating with fluorine to form a treated area
Implementation Method 3
A dielectric thin film layer can then be formed over a portion of the ultra-thin barrier layer
Implementation Method 4
utilizing pulsed deposition techniques for high-quality silicon dioxide layers
Data Source
AI summary
Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.