Selective Backside Metallization for Semiconductor Dies
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor wafers are limited in flexibility as they are either blanket-coated with backside metallization for high-power applications or fabricated without it for lidless or organic TIM applications, leading to inefficiencies and incompatibilities with varying die performance characteristics.
Innovation Solution
A method of selectively applying backside metallization to semiconductor dies based on their native clock speed and power dissipation, allowing for customized thermal management solutions, including the use of solder or organic thermal interface materials, by singulating and differentiating the metallization on individual dies within a wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If blanket backside metallization is applied to all dies on a wafer, then high-power lidded applications can be supported, but flexibility to accommodate lower-power lidless or organic TIM applications is lost
Solution Approach 1:
The patent applies local quality by selectively forming backside metallization only on specific dies that require it, rather than blanket-coating the entire wafer. This is achieved through selective die identification based on performance characteristics and targeted metallization formation processes that apply material only to selected die locations, thereby providing adaptability while avoiding unnecessary manufacturing steps on other dies.
Solution Approach 2:
The patent segments the wafer processing by dividing dies into different groups based on their performance characteristics and thermal management requirements. High-power dies are identified and separated for metallization treatment, while lower-power dies are processed differently, allowing flexible accommodation of multiple application types from a single wafer batch.
2Adaptability or versatility
If no backside metallization is applied to the wafer, then lidless or organic TIM applications are enabled, but high-power lidded applications become incompatible
Solution Approach 1:
The patent ensures thermal management reliability by providing backside metallization specifically on high-power dies that require enhanced heat dissipation, while leaving lower-power dies without metallization suitable for organic TIM or lidless applications. This localized approach maintains thermal effectiveness where needed without compromising overall application compatibility.
3Reliability
If a wafer is dedicated to high-power applications with blanket metallization, then thermal management is optimized for those applications, but waste occurs when slower dies are produced that would be better suited for other applications
Solution Approach 1:
The patent changes the parameter of metallization presence from a fixed blanket coating to a variable condition based on individual die performance characteristics. By measuring and sorting dies according to their power dissipation and clock speed, the process dynamically adjusts metallization application, ensuring thermal management optimization only where physically necessary and reducing material waste on lower-power dies.
Solution Approach 2:
The patent implements feedback through die characterization and sorting processes that measure actual performance parameters (power dissipation, clock speed) before determining metallization requirements. This feedback loop ensures that metallization is applied only to dies that truly need it, preventing material waste on slower dies that would perform better in lidless or organic TIM applications.
Data Source
AI summary
Various semiconductor workpieces with selective backside metallizations and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor workpiece that has multiple dies. A backside metallization is fabricated on a first die of the dies but not on a second die of the dies.