Selective Barrier Layer for 3D Circuit Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3-D integration of circuits faces challenges in the time-consuming formation of stitch vias and etching issues, particularly in low-K dielectric wafers, which can redistribute copper and require multiple etch processes, complicating the bonding of wafers or dies.
Innovation Solution
A method involving the formation of a selective barrier layer using cobalt or nickel on exposed portions of inter-circuit traces, extending through bonding layers to landing pads, and filling with conductive material to electrically connect the traces, simplifying the interconnect process and addressing etching complications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stitch vias are formed on the backside of donor wafer to connect interconnects in bonded wafers, then 3-D integration of wafers or dies is achieved, but the process becomes time consuming and requires additional steps
Solution Approach 1:
The patent forms openings through the donor wafer before bonding to the acceptor wafer, rather than forming stitch vias after bonding on the backside. This preliminary action eliminates the need for additional backside processing steps and reduces overall processing time while maintaining connection reliability
Solution Approach 2:
Instead of forming stitch vias on the backside of the donor wafer after bonding, the patent inverts the approach by forming openings through the donor wafer before bonding, accessing the interconnects from the frontside during the bonding process itself
2Reliability
If inter-wafer vias with differing lengths are linked on the backside of donor wafer, then interconnect connection is achieved, but the formation process becomes complex and time consuming
Solution Approach 1:
The patent merges the opening formation process with the bonding process by forming openings through the donor wafer before bonding, so that both operations are coordinated rather than performed as separate sequential steps, reducing complexity
Solution Approach 2:
The openings formed through the donor wafer serve multiple functions: they provide access to interconnects for bonding alignment and simultaneously create the inter-wafer connection paths, eliminating the need for separate stitch via formation steps
3Manufacturing precision
If etching is performed through multiple types of dielectric materials including low-K dielectrics, then inter-wafer vias are formed, but copper redistribution occurs and requires wide range of etch processes
Solution Approach 1:
The patent forms a barrier layer on the interconnect structure before etching the openings through the dielectric layers. This preliminary barrier layer prevents copper redistribution during the etching process, eliminating the need for complex etch process sequences and maintaining via formation precision
Solution Approach 2:
The barrier layer acts as an intermediary between the copper interconnect and the etch chemistry, preventing direct interaction that would cause copper redistribution while still allowing the etch process to proceed through the dielectric materials to form the required via openings
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and time required for 3-D integration by forming efficient conductive interconnects through the use of a selective barrier layer, enhancing the bonding process and minimizing copper redistribution during etching.
Implementation Method 1
Certain physical and chemical etch processes can redistribute the copper into the dielectric layers. This problem, for example, especially occurs when inter-wafer connects are used as embedded etch masks.
Implementation Method 2
filling the opening with a conductive fill material, wherein the conductive fill is electrically connected to the inter-circuit trace and the landing pad
Implementation Method 3
3-D integration of circuits is achieved using face-to-face bonding of wafers, such as acceptor wafers and donor wafers, or dies
Data Source
AI summary
A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.